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target-microblaze: Don't overuse CPUState 

Scripted conversion:
  sed -i "s/CPUState/CPUMBState/g" target-microblaze/*.[hc]
  sed -i "s/#define CPUMBState/#define CPUState/" target-microblaze/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-03-14 01:38:22 +01:00
parent 2b3e3cfe84
commit 68cee38a9c
6 changed files with 57 additions and 57 deletions
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30
target-microblaze/cpu.h
View File

@ -250,7 +250,7 @@ typedef struct CPUMBState {
#define DRTE_FLAG (1 << 17)
#define DRTB_FLAG (1 << 18)
#define D_FLAG (1 << 19) /* Bit in ESR. */
/* TB dependent CPUState. */
/* TB dependent CPUMBState. */
#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
uint32_t iflags;
@ -266,10 +266,10 @@ typedef struct CPUMBState {
CPU_COMMON
} CPUMBState;
CPUState *cpu_mb_init(const char *cpu_model);
int cpu_mb_exec(CPUState *s);
void cpu_mb_close(CPUState *s);
void do_interrupt(CPUState *env);
CPUMBState *cpu_mb_init(const char *cpu_model);
int cpu_mb_exec(CPUMBState *s);
void cpu_mb_close(CPUMBState *s);
void do_interrupt(CPUMBState *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@ -305,7 +305,7 @@ enum {
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
static inline int cpu_mmu_index (CPUState *env)
static inline int cpu_mmu_index (CPUMBState *env)
{
/* Are we in nommu mode?. */
if (!(env->sregs[SR_MSR] & MSR_VM))
@ -316,12 +316,12 @@ static inline int cpu_mmu_index (CPUState *env)
return MMU_KERNEL_IDX;
}
int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
static inline void cpu_clone_regs(CPUMBState *env, target_ulong newsp)
{
if (newsp)
env->regs[R_SP] = newsp;
@ -329,23 +329,23 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
}
#endif
static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
static inline void cpu_set_tls(CPUMBState *env, target_ulong newtls)
{
}
static inline int cpu_interrupts_enabled(CPUState *env)
static inline int cpu_interrupts_enabled(CPUMBState *env)
{
return env->sregs[SR_MSR] & MSR_IE;
}
#include "cpu-all.h"
static inline target_ulong cpu_get_pc(CPUState *env)
static inline target_ulong cpu_get_pc(CPUMBState *env)
{
return env->sregs[SR_PC];
}
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->sregs[SR_PC];
@ -355,18 +355,18 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
}
#if !defined(CONFIG_USER_ONLY)
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size);
#endif
static inline bool cpu_has_work(CPUState *env)
static inline bool cpu_has_work(CPUMBState *env)
{
return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
static inline void cpu_pc_from_tb(CPUMBState *env, TranslationBlock *tb)
{
env->sregs[SR_PC] = tb->pc;
}

10
target-microblaze/helper.c
View File

@ -25,13 +25,13 @@
#if defined(CONFIG_USER_ONLY)
void do_interrupt (CPUState *env)
void do_interrupt (CPUMBState *env)
{
env->exception_index = -1;
env->regs[14] = env->sregs[SR_PC];
}
int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
int mmu_idx)
{
env->exception_index = 0xaa;
@ -41,7 +41,7 @@ int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
#else /* !CONFIG_USER_ONLY */
int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
int mmu_idx)
{
unsigned int hit;
@ -107,7 +107,7 @@ int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
return r;
}
void do_interrupt(CPUState *env)
void do_interrupt(CPUMBState *env)
{
uint32_t t;
@ -255,7 +255,7 @@ void do_interrupt(CPUState *env)
}
}
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
target_phys_addr_t cpu_get_phys_page_debug(CPUMBState * env, target_ulong addr)
{
target_ulong vaddr, paddr = 0;
struct microblaze_mmu_lookup lu;

8
target-microblaze/mmu.c
View File

@ -31,7 +31,7 @@ static unsigned int tlb_decode_size(unsigned int f)
return sizes[f];
}
static void mmu_flush_idx(CPUState *env, unsigned int idx)
static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
struct microblaze_mmu *mmu = &env->mmu;
unsigned int tlb_size;
@ -51,7 +51,7 @@ static void mmu_flush_idx(CPUState *env, unsigned int idx)
}
}
static void mmu_change_pid(CPUState *env, unsigned int newpid)
static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
{
struct microblaze_mmu *mmu = &env->mmu;
unsigned int i;
@ -175,7 +175,7 @@ done:
}
/* Writes/reads to the MMU's special regs end up here. */
uint32_t mmu_read(CPUState *env, uint32_t rn)
uint32_t mmu_read(CPUMBState *env, uint32_t rn)
{
unsigned int i;
uint32_t r;
@ -215,7 +215,7 @@ uint32_t mmu_read(CPUState *env, uint32_t rn)
return r;
}
void mmu_write(CPUState *env, uint32_t rn, uint32_t v)
void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
unsigned int i;
D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));

6
target-microblaze/mmu.h
View File

@ -82,10 +82,10 @@ struct microblaze_mmu_lookup
} err;
};
void mmu_flip_um(CPUState *env, unsigned int um);
void mmu_flip_um(CPUMBState *env, unsigned int um);
unsigned int mmu_translate(struct microblaze_mmu *mmu,
struct microblaze_mmu_lookup *lu,
target_ulong vaddr, int rw, int mmu_idx);
uint32_t mmu_read(CPUState *env, uint32_t rn);
void mmu_write(CPUState *env, uint32_t rn, uint32_t v);
uint32_t mmu_read(CPUMBState *env, uint32_t rn);
void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v);
void mmu_init(struct microblaze_mmu *mmu);

8
target-microblaze/op_helper.c
View File

@ -42,11 +42,11 @@
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
CPUMBState *saved_env;
unsigned long pc;
int ret;
@ -506,10 +506,10 @@ void helper_mmu_write(uint32_t rn, uint32_t v)
mmu_write(env, rn, v);
}
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size)
{
CPUState *saved_env;
CPUMBState *saved_env;
saved_env = env;
env = env1;

52
target-microblaze/translate.c
View File

@ -53,7 +53,7 @@ static TCGv env_iflags;
/* This is the state at translation time. */
typedef struct DisasContext {
CPUState *env;
CPUMBState *env;
target_ulong pc;
/* Decoder. */
@ -519,10 +519,10 @@ static void dec_msr(DisasContext *dc)
tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
break;
case 0x800:
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUState, slr));
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr));
break;
case 0x802:
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUState, shr));
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
break;
default:
cpu_abort(dc->env, "unknown mts reg %x\n", sr);
@ -551,10 +551,10 @@ static void dec_msr(DisasContext *dc)
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
break;
case 0x800:
tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUState, slr));
tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr));
break;
case 0x802:
tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUState, shr));
tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr));
break;
case 0x2000:
case 0x2001:
@ -571,7 +571,7 @@ static void dec_msr(DisasContext *dc)
case 0x200c:
rn = sr & 0xf;
tcg_gen_ld_tl(cpu_R[dc->rd],
cpu_env, offsetof(CPUState, pvr.regs[rn]));
cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
break;
default:
cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
@ -1222,7 +1222,7 @@ static void dec_bcc(DisasContext *dc)
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
cpu_env, offsetof(CPUState, bimm));
cpu_env, offsetof(CPUMBState, bimm));
}
if (dec_alu_op_b_is_small_imm(dc)) {
@ -1267,7 +1267,7 @@ static void dec_br(DisasContext *dc)
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
cpu_env, offsetof(CPUState, bimm));
cpu_env, offsetof(CPUMBState, bimm));
}
if (link && dc->rd)
tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
@ -1366,7 +1366,7 @@ static void dec_rts(DisasContext *dc)
dc->delayed_branch = 2;
dc->tb_flags |= D_FLAG;
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
cpu_env, offsetof(CPUState, bimm));
cpu_env, offsetof(CPUMBState, bimm));
if (i_bit) {
LOG_DIS("rtid ir=%x\n", dc->ir);
@ -1632,7 +1632,7 @@ static inline void decode(DisasContext *dc)
}
}
static void check_breakpoint(CPUState *env, DisasContext *dc)
static void check_breakpoint(CPUMBState *env, DisasContext *dc)
{
CPUBreakpoint *bp;
@ -1648,7 +1648,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
/* generate intermediate code for basic block 'tb'. */
static void
gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
int search_pc)
{
uint16_t *gen_opc_end;
@ -1850,17 +1850,17 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
assert(!dc->abort_at_next_insn);
}
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@ -1888,13 +1888,13 @@ void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n\n");
}
CPUState *cpu_mb_init (const char *cpu_model)
CPUMBState *cpu_mb_init (const char *cpu_model)
{
CPUState *env;
CPUMBState *env;
static int tcg_initialized = 0;
int i;
env = g_malloc0(sizeof(CPUState));
env = g_malloc0(sizeof(CPUMBState));
cpu_exec_init(env);
cpu_state_reset(env);
@ -1909,28 +1909,28 @@ CPUState *cpu_mb_init (const char *cpu_model)
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
env_debug = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, debug),
offsetof(CPUMBState, debug),
"debug0");
env_iflags = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, iflags),
offsetof(CPUMBState, iflags),
"iflags");
env_imm = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, imm),
offsetof(CPUMBState, imm),
"imm");
env_btarget = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, btarget),
offsetof(CPUMBState, btarget),
"btarget");
env_btaken = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, btaken),
offsetof(CPUMBState, btaken),
"btaken");
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, regs[i]),
offsetof(CPUMBState, regs[i]),
regnames[i]);
}
for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, sregs[i]),
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);
}
#define GEN_HELPER 2
@ -1939,7 +1939,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
return env;
}
void cpu_state_reset(CPUState *env)
void cpu_state_reset(CPUMBState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@ -1991,7 +1991,7 @@ void cpu_state_reset(CPUState *env)
#endif
}
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
{
env->sregs[SR_PC] = gen_opc_pc[pc_pos];
}