hw/nvram: Introduce Xilinx eFuse QOM
This introduces the QOM for Xilinx eFuse, an one-time field-programmable storage bit array. The actual mmio interface to the array varies by device families and will be provided in different change-sets. Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Tong Ho <tong.ho@xilinx.com> Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tong Ho
Peter Maydell
parent
9fcd15b919
commit
68fbcc344e
@ -15,3 +15,10 @@ config NMC93XX_EEPROM
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config CHRP_NVRAM
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bool
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config XLNX_EFUSE_CRC
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bool
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config XLNX_EFUSE
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bool
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select XLNX_EFUSE_CRC
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@ -9,5 +9,7 @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
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softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
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softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
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softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
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softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
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specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
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119
hw/nvram/xlnx-efuse-crc.c
Normal file
119
hw/nvram/xlnx-efuse-crc.c
Normal file
@ -0,0 +1,119 @@
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/*
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* Xilinx eFuse/bbram CRC calculator
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*
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* Copyright (c) 2021 Xilinx Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/nvram/xlnx-efuse.h"
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static uint32_t xlnx_efuse_u37_crc(uint32_t prev_crc, uint32_t data,
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uint32_t addr)
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{
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/* A table for 7-bit slicing */
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static const uint32_t crc_tab[128] = {
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0x00000000, 0xe13b70f7, 0xc79a971f, 0x26a1e7e8,
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0x8ad958cf, 0x6be22838, 0x4d43cfd0, 0xac78bf27,
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0x105ec76f, 0xf165b798, 0xd7c45070, 0x36ff2087,
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0x9a879fa0, 0x7bbcef57, 0x5d1d08bf, 0xbc267848,
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0x20bd8ede, 0xc186fe29, 0xe72719c1, 0x061c6936,
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0xaa64d611, 0x4b5fa6e6, 0x6dfe410e, 0x8cc531f9,
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0x30e349b1, 0xd1d83946, 0xf779deae, 0x1642ae59,
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0xba3a117e, 0x5b016189, 0x7da08661, 0x9c9bf696,
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0x417b1dbc, 0xa0406d4b, 0x86e18aa3, 0x67dafa54,
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0xcba24573, 0x2a993584, 0x0c38d26c, 0xed03a29b,
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0x5125dad3, 0xb01eaa24, 0x96bf4dcc, 0x77843d3b,
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0xdbfc821c, 0x3ac7f2eb, 0x1c661503, 0xfd5d65f4,
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0x61c69362, 0x80fde395, 0xa65c047d, 0x4767748a,
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0xeb1fcbad, 0x0a24bb5a, 0x2c855cb2, 0xcdbe2c45,
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0x7198540d, 0x90a324fa, 0xb602c312, 0x5739b3e5,
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0xfb410cc2, 0x1a7a7c35, 0x3cdb9bdd, 0xdde0eb2a,
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0x82f63b78, 0x63cd4b8f, 0x456cac67, 0xa457dc90,
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0x082f63b7, 0xe9141340, 0xcfb5f4a8, 0x2e8e845f,
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0x92a8fc17, 0x73938ce0, 0x55326b08, 0xb4091bff,
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0x1871a4d8, 0xf94ad42f, 0xdfeb33c7, 0x3ed04330,
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0xa24bb5a6, 0x4370c551, 0x65d122b9, 0x84ea524e,
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0x2892ed69, 0xc9a99d9e, 0xef087a76, 0x0e330a81,
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0xb21572c9, 0x532e023e, 0x758fe5d6, 0x94b49521,
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0x38cc2a06, 0xd9f75af1, 0xff56bd19, 0x1e6dcdee,
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0xc38d26c4, 0x22b65633, 0x0417b1db, 0xe52cc12c,
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0x49547e0b, 0xa86f0efc, 0x8ecee914, 0x6ff599e3,
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0xd3d3e1ab, 0x32e8915c, 0x144976b4, 0xf5720643,
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0x590ab964, 0xb831c993, 0x9e902e7b, 0x7fab5e8c,
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0xe330a81a, 0x020bd8ed, 0x24aa3f05, 0xc5914ff2,
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0x69e9f0d5, 0x88d28022, 0xae7367ca, 0x4f48173d,
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0xf36e6f75, 0x12551f82, 0x34f4f86a, 0xd5cf889d,
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0x79b737ba, 0x988c474d, 0xbe2da0a5, 0x5f16d052
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};
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/*
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* eFuse calculation is shown here:
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* https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1496
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*
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* Each u32 word is appended a 5-bit value, for a total of 37 bits; see:
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* https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1356
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*/
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uint32_t crc = prev_crc;
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const unsigned rshf = 7;
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const uint32_t im = (1 << rshf) - 1;
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const uint32_t rm = (1 << (32 - rshf)) - 1;
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const uint32_t i2 = (1 << 2) - 1;
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const uint32_t r2 = (1 << 30) - 1;
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unsigned j;
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uint32_t i, r;
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uint64_t w;
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w = (uint64_t)(addr) << 32;
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w |= data;
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/* Feed 35 bits, in 5 rounds, each a slice of 7 bits */
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for (j = 0; j < 5; j++) {
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r = rm & (crc >> rshf);
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i = im & (crc ^ w);
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crc = crc_tab[i] ^ r;
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w >>= rshf;
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}
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/* Feed the remaining 2 bits */
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r = r2 & (crc >> 2);
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i = i2 & (crc ^ w);
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crc = crc_tab[i << (rshf - 2)] ^ r;
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return crc;
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}
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uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
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unsigned zpads)
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{
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uint32_t crc = 0;
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unsigned index;
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for (index = zpads; index; index--) {
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crc = xlnx_efuse_u37_crc(crc, 0, (index + u32_cnt));
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}
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for (index = u32_cnt; index; index--) {
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crc = xlnx_efuse_u37_crc(crc, data[index - 1], index);
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}
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return crc;
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}
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280
hw/nvram/xlnx-efuse.c
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280
hw/nvram/xlnx-efuse.c
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@ -0,0 +1,280 @@
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/*
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* QEMU model of the EFUSE eFuse
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*
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* Copyright (c) 2015 Xilinx Inc.
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*
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* Written by Edgar E. Iglesias <edgari@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/nvram/xlnx-efuse.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "sysemu/blockdev.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#define TBIT0_OFFSET 28
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#define TBIT1_OFFSET 29
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#define TBIT2_OFFSET 30
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#define TBIT3_OFFSET 31
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#define TBITS_PATTERN (0x0AU << TBIT0_OFFSET)
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#define TBITS_MASK (0x0FU << TBIT0_OFFSET)
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bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit)
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{
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bool b = s->fuse32[bit / 32] & (1 << (bit % 32));
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return b;
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}
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static int efuse_bytes(XlnxEFuse *s)
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{
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return ROUND_UP((s->efuse_nr * s->efuse_size) / 8, 4);
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}
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static int efuse_bdrv_read(XlnxEFuse *s, Error **errp)
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{
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uint32_t *ram = s->fuse32;
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int nr = efuse_bytes(s);
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if (!s->blk) {
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return 0;
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}
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s->blk_ro = !blk_supports_write_perm(s->blk);
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if (!s->blk_ro) {
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int rc;
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rc = blk_set_perm(s->blk,
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(BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
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BLK_PERM_ALL, NULL);
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if (rc) {
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s->blk_ro = true;
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}
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}
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if (s->blk_ro) {
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warn_report("%s: Skip saving updates to read-only eFUSE backstore.",
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blk_name(s->blk));
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}
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if (blk_pread(s->blk, 0, ram, nr) < 0) {
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error_setg(errp, "%s: Failed to read %u bytes from eFUSE backstore.",
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blk_name(s->blk), nr);
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return -1;
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}
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/* Convert from little-endian backstore for each 32-bit row */
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nr /= 4;
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while (nr--) {
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ram[nr] = le32_to_cpu(ram[nr]);
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}
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return 0;
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}
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static void efuse_bdrv_sync(XlnxEFuse *s, unsigned int bit)
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{
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unsigned int row_offset;
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uint32_t le32;
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if (!s->blk || s->blk_ro) {
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return; /* Silent on read-only backend to avoid message flood */
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}
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/* Backstore is always in little-endian */
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le32 = cpu_to_le32(xlnx_efuse_get_row(s, bit));
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row_offset = (bit / 32) * 4;
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if (blk_pwrite(s->blk, row_offset, &le32, 4, 0) < 0) {
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error_report("%s: Failed to write offset %u of eFUSE backstore.",
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blk_name(s->blk), row_offset);
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}
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}
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static int efuse_ro_bits_cmp(const void *a, const void *b)
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{
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uint32_t i = *(const uint32_t *)a;
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uint32_t j = *(const uint32_t *)b;
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return (i > j) - (i < j);
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}
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static void efuse_ro_bits_sort(XlnxEFuse *s)
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{
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uint32_t *ary = s->ro_bits;
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const uint32_t cnt = s->ro_bits_cnt;
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if (ary && cnt > 1) {
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qsort(ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp);
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}
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}
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static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
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{
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const uint32_t *ary = s->ro_bits;
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const uint32_t cnt = s->ro_bits_cnt;
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if (!ary || !cnt) {
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return false;
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}
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return bsearch(&k, ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp) != NULL;
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}
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bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
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{
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if (efuse_ro_bits_find(s, bit)) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: "
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"Ignored setting of readonly efuse bit<%u,%u>!\n",
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object_get_canonical_path(OBJECT(s)),
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(bit / 32), (bit % 32));
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return false;
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}
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s->fuse32[bit / 32] |= 1 << (bit % 32);
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efuse_bdrv_sync(s, bit);
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return true;
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}
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bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start)
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{
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uint32_t calc;
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/* A key always occupies multiple of whole rows */
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assert((start % 32) == 0);
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calc = xlnx_efuse_calc_crc(&s->fuse32[start / 32], (256 / 32), 0);
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return calc == crc;
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}
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uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s)
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{
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int nr;
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uint32_t check = 0;
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for (nr = s->efuse_nr; nr-- > 0; ) {
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int efuse_start_row_num = (s->efuse_size * nr) / 32;
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uint32_t data = s->fuse32[efuse_start_row_num];
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/*
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* If the option is on, auto-init blank T-bits.
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* (non-blank will still be reported as '0' in the check, e.g.,
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* for error-injection tests)
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*/
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if ((data & TBITS_MASK) == 0 && s->init_tbits) {
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data |= TBITS_PATTERN;
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s->fuse32[efuse_start_row_num] = data;
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efuse_bdrv_sync(s, (efuse_start_row_num * 32 + TBIT0_OFFSET));
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}
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check = (check << 1) | ((data & TBITS_MASK) == TBITS_PATTERN);
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}
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return check;
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}
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static void efuse_realize(DeviceState *dev, Error **errp)
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{
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XlnxEFuse *s = XLNX_EFUSE(dev);
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/* Sort readonly-list for bsearch lookup */
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efuse_ro_bits_sort(s);
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if ((s->efuse_size % 32) != 0) {
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error_setg(errp,
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"%s.efuse-size: %u: property value not multiple of 32.",
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object_get_canonical_path(OBJECT(dev)), s->efuse_size);
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return;
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}
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s->fuse32 = g_malloc0(efuse_bytes(s));
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if (efuse_bdrv_read(s, errp)) {
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g_free(s->fuse32);
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}
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}
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static void efuse_prop_set_drive(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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DeviceState *dev = DEVICE(obj);
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qdev_prop_drive.set(obj, v, name, opaque, errp);
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/* Fill initial data if backend is attached after realized */
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if (dev->realized) {
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efuse_bdrv_read(XLNX_EFUSE(obj), errp);
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}
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}
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static void efuse_prop_get_drive(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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qdev_prop_drive.get(obj, v, name, opaque, errp);
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}
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static void efuse_prop_release_drive(Object *obj, const char *name,
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void *opaque)
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{
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qdev_prop_drive.release(obj, name, opaque);
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}
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static const PropertyInfo efuse_prop_drive = {
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.name = "str",
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.description = "Node name or ID of a block device to use as eFUSE backend",
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.realized_set_allowed = true,
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.get = efuse_prop_get_drive,
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.set = efuse_prop_set_drive,
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.release = efuse_prop_release_drive,
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};
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static Property efuse_properties[] = {
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||||
DEFINE_PROP("drive", XlnxEFuse, blk, efuse_prop_drive, BlockBackend *),
|
||||
DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3),
|
||||
DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32),
|
||||
DEFINE_PROP_BOOL("init-factory-tbits", XlnxEFuse, init_tbits, true),
|
||||
DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits,
|
||||
qdev_prop_uint32, uint32_t),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void efuse_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->realize = efuse_realize;
|
||||
device_class_set_props(dc, efuse_properties);
|
||||
}
|
||||
|
||||
static const TypeInfo efuse_info = {
|
||||
.name = TYPE_XLNX_EFUSE,
|
||||
.parent = TYPE_DEVICE,
|
||||
.instance_size = sizeof(XlnxEFuse),
|
||||
.class_init = efuse_class_init,
|
||||
};
|
||||
|
||||
static void efuse_register_types(void)
|
||||
{
|
||||
type_register_static(&efuse_info);
|
||||
}
|
||||
type_init(efuse_register_types)
|
||||
132
include/hw/nvram/xlnx-efuse.h
Normal file
132
include/hw/nvram/xlnx-efuse.h
Normal file
@ -0,0 +1,132 @@
|
||||
/*
|
||||
* QEMU model of the Xilinx eFuse core
|
||||
*
|
||||
* Copyright (c) 2015 Xilinx Inc.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgari@xilinx.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XLNX_EFUSE_H
|
||||
#define XLNX_EFUSE_H
|
||||
|
||||
#include "sysemu/block-backend.h"
|
||||
#include "hw/qdev-core.h"
|
||||
|
||||
#define TYPE_XLNX_EFUSE "xlnx,efuse"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxEFuse, XLNX_EFUSE);
|
||||
|
||||
struct XlnxEFuse {
|
||||
DeviceState parent_obj;
|
||||
BlockBackend *blk;
|
||||
bool blk_ro;
|
||||
uint32_t *fuse32;
|
||||
|
||||
DeviceState *dev;
|
||||
|
||||
bool init_tbits;
|
||||
|
||||
uint8_t efuse_nr;
|
||||
uint32_t efuse_size;
|
||||
|
||||
uint32_t *ro_bits;
|
||||
uint32_t ro_bits_cnt;
|
||||
};
|
||||
|
||||
/**
|
||||
* xlnx_efuse_calc_crc:
|
||||
* @data: an array of 32-bit words for which the CRC should be computed
|
||||
* @u32_cnt: the array size in number of 32-bit words
|
||||
* @zpads: the number of 32-bit zeros prepended to @data before computation
|
||||
*
|
||||
* This function is used to compute the CRC for an array of 32-bit words,
|
||||
* using a Xilinx-specific data padding.
|
||||
*
|
||||
* Returns: the computed 32-bit CRC
|
||||
*/
|
||||
uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
|
||||
unsigned zpads);
|
||||
|
||||
/**
|
||||
* xlnx_efuse_get_bit:
|
||||
* @s: the efuse object
|
||||
* @bit: the efuse bit-address to read the data
|
||||
*
|
||||
* Returns: the bit, 0 or 1, at @bit of object @s
|
||||
*/
|
||||
bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit);
|
||||
|
||||
/**
|
||||
* xlnx_efuse_set_bit:
|
||||
* @s: the efuse object
|
||||
* @bit: the efuse bit-address to be written a value of 1
|
||||
*
|
||||
* Returns: true on success, false on failure
|
||||
*/
|
||||
bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit);
|
||||
|
||||
/**
|
||||
* xlnx_efuse_k256_check:
|
||||
* @s: the efuse object
|
||||
* @crc: the 32-bit CRC to be compared with
|
||||
* @start: the efuse bit-address (which must be multiple of 32) of the
|
||||
* start of a 256-bit array
|
||||
*
|
||||
* This function computes the CRC of a 256-bit array starting at @start
|
||||
* then compares to the given @crc
|
||||
*
|
||||
* Returns: true of @crc == computed, false otherwise
|
||||
*/
|
||||
bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start);
|
||||
|
||||
/**
|
||||
* xlnx_efuse_tbits_check:
|
||||
* @s: the efuse object
|
||||
*
|
||||
* This function inspects a number of efuse bits at specific addresses
|
||||
* to see if they match a validation pattern. Each pattern is a group
|
||||
* of 4 bits, and there are 3 groups.
|
||||
*
|
||||
* Returns: a 3-bit mask, where a bit of '1' means the corresponding
|
||||
* group has a valid pattern.
|
||||
*/
|
||||
uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s);
|
||||
|
||||
/**
|
||||
* xlnx_efuse_get_row:
|
||||
* @s: the efuse object
|
||||
* @bit: the efuse bit address for which a 32-bit value is read
|
||||
*
|
||||
* Returns: the entire 32 bits of the efuse, starting at a bit
|
||||
* address that is multiple of 32 and contains the bit at @bit
|
||||
*/
|
||||
static inline uint32_t xlnx_efuse_get_row(XlnxEFuse *s, unsigned int bit)
|
||||
{
|
||||
if (!(s->fuse32)) {
|
||||
return 0;
|
||||
} else {
|
||||
unsigned int row_idx = bit / 32;
|
||||
|
||||
assert(row_idx < (s->efuse_size * s->efuse_nr / 32));
|
||||
return s->fuse32[row_idx];
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user