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hw/intc/loongson_liointc: Fix per core ISR handling

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Per core ISR is a set of 32-bit registers spaced by 8 bytes.
This patch fixed calculation of it's size and also added check
of alignment at reading & writing.

Fixes: Coverity CID 1438965 and CID 1438967
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20210112012527.28927-1-jiaxun.yang@flygoat.com>
[PMD: Added Coverity CID]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Jiaxun Yang 2021-01-12 09:25:27 +08:00 committed by Philippe Mathieu-Daudé
parent 283eae174e
commit 6902759965
1 changed files with 13 additions and 3 deletions
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16
hw/intc/loongson_liointc.c
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@ -41,7 +41,7 @@
#define R_IEN_CLR 0x2c
#define R_ISR_SIZE 0x8
#define R_START 0x40
#define R_END 0x64
#define R_END (R_START + R_ISR_SIZE * NUM_CORES)
struct loongson_liointc {
SysBusDevice parent_obj;
@ -125,7 +125,12 @@ liointc_read(void *opaque, hwaddr addr, unsigned int size)
}
if (addr >= R_START && addr < R_END) {
int core = (addr - R_START) / R_ISR_SIZE;
hwaddr offset = addr - R_START;
int core = offset / R_ISR_SIZE;
if (offset % R_ISR_SIZE) {
goto out;
}
r = p->per_core_isr[core];
goto out;
}
@ -169,7 +174,12 @@ liointc_write(void *opaque, hwaddr addr,
}
if (addr >= R_START && addr < R_END) {
int core = (addr - R_START) / R_ISR_SIZE;
hwaddr offset = addr - R_START;
int core = offset / R_ISR_SIZE;
if (offset % R_ISR_SIZE) {
goto out;
}
p->per_core_isr[core] = value;
goto out;
}