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target/riscv: Allow AIA device emulation to set ireg rmw callback 

The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-9-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-02-04 23:16:44 +05:30 committed by Alistair Francis
parent aa7508bbc6
commit 69077dd687
2 changed files with 37 additions and 0 deletions
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23
target/riscv/cpu.h
View File

@ -256,6 +256,22 @@ struct CPURISCVState {
uint64_t (*rdtime_fn)(uint32_t);
uint32_t rdtime_fn_arg;
/* machine specific AIA ireg read-modify-write callback */
#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
((((__xlen) & 0xff) << 24) | \
(((__vgein) & 0x3f) << 20) | \
(((__virt) & 0x1) << 18) | \
(((__priv) & 0x3) << 16) | \
(__isel & 0xffff))
#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1)
#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f)
#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff)
int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
target_ulong *val, target_ulong new_val, target_ulong write_mask);
void *aia_ireg_rmw_fn_arg[4];
/* True if in debugger mode. */
bool debugger;
@ -433,6 +449,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
uint32_t arg);
void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
int (*rmw_fn)(void *arg,
target_ulong reg,
target_ulong *val,
target_ulong new_val,
target_ulong write_mask),
void *rmw_fn_arg);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);

14
target/riscv/cpu_helper.c
View File

@ -396,6 +396,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
env->rdtime_fn_arg = arg;
}
void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
int (*rmw_fn)(void *arg,
target_ulong reg,
target_ulong *val,
target_ulong new_val,
target_ulong write_mask),
void *rmw_fn_arg)
{
if (priv <= PRV_M) {
env->aia_ireg_rmw_fn[priv] = rmw_fn;
env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
}
}
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {