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target/arm: Set TCR_EL1.TSZ for user-only

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Set this as the kernel would, to 48 bits, to keep the computation
of the address space correct for PAuth.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-03-01 11:59:42 -10:00 committed by Peter Maydell
parent d5e51efb9f
commit 691f1ffdfc
1 changed files with 2 additions and 1 deletions
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3
target/arm/cpu.c
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@ -206,10 +206,11 @@ static void arm_cpu_reset(DeviceState *dev)
aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
}
/*
* Enable 48-bit address space (TODO: take reserved_va into account).
* Enable TBI0 but not TBI1.
* Note that this must match useronly_clean_ptr.
*/
env->cp15.tcr_el[1].raw_tcr = (1ULL << 37);
env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37);
/* Enable MTE */
if (cpu_isar_feature(aa64_mte, cpu)) {