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ppc/ppc405: QOM'ify PLB

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PLB is currently modeled as a simple DCR device. Also drop the
ppc4xx_plb_init() helper and adapt the sam460ex machine.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <c4256d1bffca86fe1d696aa9c56732e5f563e114.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2022-08-17 17:08:28 +02:00 committed by Daniel Henrique Barboza
parent 2841430e6a
commit 695bce07dc
3 changed files with 50 additions and 30 deletions
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14
hw/ppc/ppc405.h
View File

@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
/* Peripheral local bus arbitrer */
#define TYPE_PPC405_PLB "ppc405-plb"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
struct Ppc405PlbState {
Ppc4xxDcrDeviceState parent_obj;
uint32_t acr;
uint32_t bear;
uint32_t besr;
};
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@ -232,11 +243,10 @@ struct Ppc405SoCState {
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
Ppc405PlbState plb;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
#endif /* PPC405_H */

62
hw/ppc/ppc405_uc.c
View File

@ -148,19 +148,11 @@ enum {
PLB4A1_ACR = 0x089,
};
typedef struct ppc4xx_plb_t ppc4xx_plb_t;
struct ppc4xx_plb_t {
uint32_t acr;
uint32_t bear;
uint32_t besr;
};
static uint32_t dcr_read_plb (void *opaque, int dcrn)
static uint32_t dcr_read_plb(void *opaque, int dcrn)
{
ppc4xx_plb_t *plb;
Ppc405PlbState *plb = opaque;
uint32_t ret;
plb = opaque;
switch (dcrn) {
case PLB0_ACR:
ret = plb->acr;
@ -180,11 +172,10 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn)
return ret;
}
static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
{
ppc4xx_plb_t *plb;
Ppc405PlbState *plb = opaque;
plb = opaque;
switch (dcrn) {
case PLB0_ACR:
/* We don't care about the actual parameters written as
@ -202,28 +193,36 @@ static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
}
}
static void ppc4xx_plb_reset (void *opaque)
static void ppc405_plb_reset(DeviceState *dev)
{
ppc4xx_plb_t *plb;
Ppc405PlbState *plb = PPC405_PLB(dev);
plb = opaque;
plb->acr = 0x00000000;
plb->bear = 0x00000000;
plb->besr = 0x00000000;
}
void ppc4xx_plb_init(CPUPPCState *env)
static void ppc405_plb_realize(DeviceState *dev, Error **errp)
{
ppc4xx_plb_t *plb;
Ppc405PlbState *plb = PPC405_PLB(dev);
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
plb = g_new0(ppc4xx_plb_t, 1);
ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
qemu_register_reset(ppc4xx_plb_reset, plb);
ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
}
static void ppc405_plb_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = ppc405_plb_realize;
dc->reset = ppc405_plb_reset;
/* Reason: only works as function of a ppc4xx SoC */
dc->user_creatable = false;
}
/*****************************************************************************/
@ -1374,6 +1373,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
}
static void ppc405_reset(void *opaque)
@ -1405,7 +1406,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* PLB arbitrer */
ppc4xx_plb_init(env);
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->plb), &s->cpu, errp)) {
return;
}
/* PLB to OPB bridge */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
@ -1530,6 +1533,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
.name = TYPE_PPC405_PLB,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405PlbState),
.class_init = ppc405_plb_class_init,
}, {
.name = TYPE_PPC405_POB,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405PobState),

4
hw/ppc/sam460ex.c
View File

@ -309,7 +309,9 @@ static void sam460ex_init(MachineState *machine)
ppc_dcr_init(env, NULL, NULL);
/* PLB arbitrer */
ppc4xx_plb_init(env);
dev = qdev_new(TYPE_PPC405_PLB);
ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
object_unref(OBJECT(dev));
/* interrupt controllers */
for (i = 0; i < ARRAY_SIZE(uic); i++) {