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target/riscv: Fix privilege mode of G-stage translation for debugging

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G-stage translation should be considered to be user-level access in
riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill().

This fixes a bug that prevents gdb from reading memory while the VM is
running in VS-mode.

Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240228081028.35081-1-hrak1529@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Hiroaki Yamamoto 2024-02-28 17:10:28 +09:00 committed by Alistair Francis
parent 0678e9f29c
commit 6979b7b3f2
1 changed files with 1 additions and 1 deletions
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2
target/riscv/cpu_helper.c
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@ -1223,7 +1223,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
if (env->virt_enabled) {
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
0, mmu_idx, false, true, true)) {
0, MMUIdx_U, false, true, true)) {
return -1;
}
}