target-ppc: pass DisasContext to SPR generator functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
2cbcfb281a
commit
69b058c881
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@ -320,6 +320,7 @@ typedef struct opc_handler_t opc_handler_t;
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/*****************************************************************************/
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/* Types used to describe some PowerPC registers */
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typedef struct CPUPPCState CPUPPCState;
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typedef struct DisasContext DisasContext;
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typedef struct ppc_tb_t ppc_tb_t;
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typedef struct ppc_spr_t ppc_spr_t;
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typedef struct ppc_dcr_t ppc_dcr_t;
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@ -328,13 +329,13 @@ typedef union ppc_tlb_t ppc_tlb_t;
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/* SPR access micro-ops generations callbacks */
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struct ppc_spr_t {
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void (*uea_read)(void *opaque, int gpr_num, int spr_num);
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void (*uea_write)(void *opaque, int spr_num, int gpr_num);
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void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
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void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
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#if !defined(CONFIG_USER_ONLY)
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void (*oea_read)(void *opaque, int gpr_num, int spr_num);
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void (*oea_write)(void *opaque, int spr_num, int gpr_num);
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void (*hea_read)(void *opaque, int gpr_num, int spr_num);
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void (*hea_write)(void *opaque, int spr_num, int gpr_num);
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void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
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void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
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void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
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void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
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#endif
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const char *name;
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target_ulong default_value;
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@ -183,7 +183,7 @@ void ppc_translate_init(void)
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}
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/* internal defines */
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typedef struct DisasContext {
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struct DisasContext {
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struct TranslationBlock *tb;
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target_ulong nip;
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uint32_t opcode;
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@ -207,7 +207,7 @@ typedef struct DisasContext {
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int singlestep_enabled;
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uint64_t insns_flags;
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uint64_t insns_flags2;
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} DisasContext;
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};
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/* Return true iff byteswap is needed in a scalar memop */
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static inline bool need_byteswap(const DisasContext *ctx)
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@ -4206,7 +4206,7 @@ static void gen_mfmsr(DisasContext *ctx)
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#endif
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}
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static void spr_noaccess(void *opaque, int gprn, int sprn)
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static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
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{
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#if 0
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sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
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@ -4218,7 +4218,7 @@ static void spr_noaccess(void *opaque, int gprn, int sprn)
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/* mfspr */
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static inline void gen_op_mfspr(DisasContext *ctx)
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{
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void (*read_cb)(void *opaque, int gprn, int sprn);
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void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
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uint32_t sprn = SPR(ctx->opcode);
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#if !defined(CONFIG_USER_ONLY)
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@ -4369,7 +4369,7 @@ static void gen_mtmsr(DisasContext *ctx)
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/* mtspr */
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static void gen_mtspr(DisasContext *ctx)
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{
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void (*write_cb)(void *opaque, int sprn, int gprn);
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void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
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uint32_t sprn = SPR(ctx->opcode);
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#if !defined(CONFIG_USER_ONLY)
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@ -65,7 +65,7 @@ static void spr_load_dump_spr(int sprn)
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#endif
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}
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static void spr_read_generic (void *opaque, int gprn, int sprn)
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static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
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{
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gen_load_spr(cpu_gpr[gprn], sprn);
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spr_load_dump_spr(sprn);
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@ -80,14 +80,14 @@ static void spr_store_dump_spr(int sprn)
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#endif
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}
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static void spr_write_generic (void *opaque, int sprn, int gprn)
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static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
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{
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gen_store_spr(sprn, cpu_gpr[gprn]);
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spr_store_dump_spr(sprn);
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}
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_generic32(void *opaque, int sprn, int gprn)
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static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
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{
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#ifdef TARGET_PPC64
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TCGv t0 = tcg_temp_new();
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@ -96,11 +96,11 @@ static void spr_write_generic32(void *opaque, int sprn, int gprn)
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tcg_temp_free(t0);
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spr_store_dump_spr(sprn);
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#else
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spr_write_generic(opaque, sprn, gprn);
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spr_write_generic(ctx, sprn, gprn);
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#endif
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}
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static void spr_write_clear (void *opaque, int sprn, int gprn)
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static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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@ -112,7 +112,7 @@ static void spr_write_clear (void *opaque, int sprn, int gprn)
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tcg_temp_free(t1);
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}
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static void spr_access_nop(void *opaque, int sprn, int gprn)
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static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
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{
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}
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@ -120,47 +120,47 @@ static void spr_access_nop(void *opaque, int sprn, int gprn)
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/* SPR common to all PowerPC */
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/* XER */
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static void spr_read_xer (void *opaque, int gprn, int sprn)
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static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
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{
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gen_read_xer(cpu_gpr[gprn]);
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}
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static void spr_write_xer (void *opaque, int sprn, int gprn)
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static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
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{
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gen_write_xer(cpu_gpr[gprn]);
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}
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/* LR */
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static void spr_read_lr (void *opaque, int gprn, int sprn)
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static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
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}
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static void spr_write_lr (void *opaque, int sprn, int gprn)
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static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
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{
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tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
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}
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/* CFAR */
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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static void spr_read_cfar (void *opaque, int gprn, int sprn)
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static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
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}
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static void spr_write_cfar (void *opaque, int sprn, int gprn)
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static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
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{
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tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
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}
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#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
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/* CTR */
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static void spr_read_ctr (void *opaque, int gprn, int sprn)
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static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
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}
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static void spr_write_ctr (void *opaque, int sprn, int gprn)
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static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
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{
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tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
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}
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@ -171,13 +171,13 @@ static void spr_write_ctr (void *opaque, int sprn, int gprn)
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/* UPMCx */
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/* USIA */
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/* UDECR */
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static void spr_read_ureg (void *opaque, int gprn, int sprn)
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static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
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{
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gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
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}
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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static void spr_write_ureg(void *opaque, int sprn, int gprn)
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static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
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{
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gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
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}
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@ -186,7 +186,7 @@ static void spr_write_ureg(void *opaque, int sprn, int gprn)
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/* SPR common to all non-embedded PowerPC */
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/* DECR */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_decr (void *opaque, int gprn, int sprn)
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static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
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{
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if (use_icount) {
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gen_io_start();
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@ -194,11 +194,11 @@ static void spr_read_decr (void *opaque, int gprn, int sprn)
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gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
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if (use_icount) {
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gen_io_end();
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gen_stop_exception(opaque);
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gen_stop_exception(ctx);
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}
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}
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static void spr_write_decr (void *opaque, int sprn, int gprn)
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static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
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{
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if (use_icount) {
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gen_io_start();
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@ -206,14 +206,14 @@ static void spr_write_decr (void *opaque, int sprn, int gprn)
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gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
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if (use_icount) {
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gen_io_end();
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gen_stop_exception(opaque);
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gen_stop_exception(ctx);
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}
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}
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#endif
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/* SPR common to all non-embedded PowerPC, except 601 */
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/* Time base */
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static void spr_read_tbl (void *opaque, int gprn, int sprn)
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static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
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{
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if (use_icount) {
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gen_io_start();
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@ -221,11 +221,11 @@ static void spr_read_tbl (void *opaque, int gprn, int sprn)
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gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
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if (use_icount) {
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gen_io_end();
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gen_stop_exception(opaque);
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gen_stop_exception(ctx);
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}
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}
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static void spr_read_tbu (void *opaque, int gprn, int sprn)
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static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
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{
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if (use_icount) {
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gen_io_start();
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@ -233,24 +233,24 @@ static void spr_read_tbu (void *opaque, int gprn, int sprn)
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gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
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if (use_icount) {
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gen_io_end();
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gen_stop_exception(opaque);
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gen_stop_exception(ctx);
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}
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}
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__attribute__ (( unused ))
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static void spr_read_atbl (void *opaque, int gprn, int sprn)
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static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
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{
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gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
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}
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__attribute__ (( unused ))
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static void spr_read_atbu (void *opaque, int gprn, int sprn)
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static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
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{
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gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
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}
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_tbl (void *opaque, int sprn, int gprn)
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static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
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{
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if (use_icount) {
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gen_io_start();
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@ -258,11 +258,11 @@ static void spr_write_tbl (void *opaque, int sprn, int gprn)
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gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
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if (use_icount) {
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gen_io_end();
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gen_stop_exception(opaque);
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gen_stop_exception(ctx);
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}
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}
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static void spr_write_tbu (void *opaque, int sprn, int gprn)
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static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
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{
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if (use_icount) {
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gen_io_start();
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@ -270,25 +270,25 @@ static void spr_write_tbu (void *opaque, int sprn, int gprn)
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gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
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if (use_icount) {
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gen_io_end();
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gen_stop_exception(opaque);
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gen_stop_exception(ctx);
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}
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}
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__attribute__ (( unused ))
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static void spr_write_atbl (void *opaque, int sprn, int gprn)
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static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
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{
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gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
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}
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__attribute__ (( unused ))
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static void spr_write_atbu (void *opaque, int sprn, int gprn)
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static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
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{
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gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
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}
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#if defined(TARGET_PPC64)
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__attribute__ (( unused ))
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static void spr_read_purr (void *opaque, int gprn, int sprn)
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static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
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{
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gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
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}
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@ -298,38 +298,38 @@ static void spr_read_purr (void *opaque, int gprn, int sprn)
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#if !defined(CONFIG_USER_ONLY)
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/* IBAT0U...IBAT0U */
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/* IBAT0L...IBAT7L */
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static void spr_read_ibat (void *opaque, int gprn, int sprn)
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static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
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}
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static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
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static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
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}
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static void spr_write_ibatu (void *opaque, int sprn, int gprn)
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static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
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gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
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tcg_temp_free_i32(t0);
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}
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static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
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static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
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gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
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tcg_temp_free_i32(t0);
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}
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static void spr_write_ibatl (void *opaque, int sprn, int gprn)
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static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
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gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
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tcg_temp_free_i32(t0);
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}
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static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
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static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
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gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
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@ -338,38 +338,38 @@ static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
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/* DBAT0U...DBAT7U */
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/* DBAT0L...DBAT7L */
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static void spr_read_dbat (void *opaque, int gprn, int sprn)
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static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
|
||||
}
|
||||
|
||||
static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
|
||||
}
|
||||
|
||||
static void spr_write_dbatu (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
|
||||
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
|
||||
tcg_temp_free_i32(t0);
|
||||
}
|
||||
|
||||
static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
|
||||
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
|
||||
tcg_temp_free_i32(t0);
|
||||
}
|
||||
|
||||
static void spr_write_dbatl (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
|
||||
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
|
||||
tcg_temp_free_i32(t0);
|
||||
}
|
||||
|
||||
static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
|
||||
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
|
||||
|
|
@ -377,19 +377,19 @@ static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
|
|||
}
|
||||
|
||||
/* SDR1 */
|
||||
static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
||||
/* 64 bits PowerPC specific SPRs */
|
||||
#if defined(TARGET_PPC64)
|
||||
static void spr_read_hior (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
|
||||
}
|
||||
|
||||
static void spr_write_hior (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv t0 = tcg_temp_new();
|
||||
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
|
||||
|
|
@ -401,31 +401,29 @@ static void spr_write_hior (void *opaque, int sprn, int gprn)
|
|||
|
||||
/* PowerPC 601 specific registers */
|
||||
/* RTC */
|
||||
static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
|
||||
}
|
||||
|
||||
static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
||||
static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
||||
static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
DisasContext *ctx = opaque;
|
||||
|
||||
gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
|
||||
/* Must stop the translation as endianness may have changed */
|
||||
gen_stop_exception(ctx);
|
||||
|
|
@ -434,19 +432,19 @@ static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
|
|||
|
||||
/* Unified bats */
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
|
||||
}
|
||||
|
||||
static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
|
||||
gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
|
||||
tcg_temp_free_i32(t0);
|
||||
}
|
||||
|
||||
static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
|
||||
gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
|
||||
|
|
@ -456,36 +454,34 @@ static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
|
|||
|
||||
/* PowerPC 40x specific registers */
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
|
||||
}
|
||||
|
||||
static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
||||
static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
DisasContext *ctx = opaque;
|
||||
|
||||
gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
|
||||
/* We must stop translation as we may have rebooted */
|
||||
gen_stop_exception(ctx);
|
||||
}
|
||||
|
||||
static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
||||
static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
||||
static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
|
@ -494,19 +490,19 @@ static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
|
|||
/* PowerPC 403 specific registers */
|
||||
/* PBL1 / PBU1 / PBL2 / PBU2 */
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
|
||||
}
|
||||
|
||||
static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
|
||||
gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
|
||||
tcg_temp_free_i32(t0);
|
||||
}
|
||||
|
||||
static void spr_write_pir (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv t0 = tcg_temp_new();
|
||||
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
|
||||
|
|
@ -516,7 +512,7 @@ static void spr_write_pir (void *opaque, int sprn, int gprn)
|
|||
#endif
|
||||
|
||||
/* SPE specific registers */
|
||||
static void spr_read_spefscr (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_temp_new_i32();
|
||||
tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
|
||||
|
|
@ -524,7 +520,7 @@ static void spr_read_spefscr (void *opaque, int gprn, int sprn)
|
|||
tcg_temp_free_i32(t0);
|
||||
}
|
||||
|
||||
static void spr_write_spefscr (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_temp_new_i32();
|
||||
tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
|
||||
|
|
@ -534,7 +530,7 @@ static void spr_write_spefscr (void *opaque, int sprn, int gprn)
|
|||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* Callback used to write the exception vector base */
|
||||
static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv t0 = tcg_temp_new();
|
||||
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
|
||||
|
|
@ -544,9 +540,8 @@ static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
|
|||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
DisasContext *ctx = opaque;
|
||||
int sprn_offs;
|
||||
|
||||
if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
|
||||
|
|
@ -604,12 +599,12 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
|
|||
|
||||
static inline void _spr_register(CPUPPCState *env, int num,
|
||||
const char *name,
|
||||
void (*uea_read)(void *opaque, int gprn, int sprn),
|
||||
void (*uea_write)(void *opaque, int sprn, int gprn),
|
||||
void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
|
||||
void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
|
||||
void (*oea_read)(void *opaque, int gprn, int sprn),
|
||||
void (*oea_write)(void *opaque, int sprn, int gprn),
|
||||
void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
|
||||
void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
|
||||
#endif
|
||||
#if defined(CONFIG_KVM)
|
||||
uint64_t one_reg_id,
|
||||
|
|
@ -1040,19 +1035,19 @@ static void gen_spr_7xx (CPUPPCState *env)
|
|||
|
||||
#ifdef TARGET_PPC64
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
static void spr_read_uamr (void *opaque, int gprn, int sprn)
|
||||
static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_load_spr(cpu_gpr[gprn], SPR_AMR);
|
||||
spr_load_dump_spr(SPR_AMR);
|
||||
}
|
||||
|
||||
static void spr_write_uamr (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
|
||||
spr_store_dump_spr(SPR_AMR);
|
||||
}
|
||||
|
||||
static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv t0 = tcg_temp_new();
|
||||
|
||||
|
|
@ -1454,7 +1449,7 @@ static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
|
|||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv t0 = tcg_temp_new();
|
||||
|
||||
|
|
@ -1463,7 +1458,7 @@ static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
|
|||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn)
|
||||
static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv t0 = tcg_temp_new();
|
||||
|
||||
|
|
@ -1472,12 +1467,12 @@ static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn)
|
|||
tcg_temp_free(t0);
|
||||
}
|
||||
|
||||
static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
|
||||
}
|
||||
|
||||
static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
|
||||
static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32(sprn);
|
||||
gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
|
||||
|
|
@ -1693,7 +1688,7 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
|
|||
/* TLB assist registers */
|
||||
/* XXX : not implemented */
|
||||
for (i = 0; i < 8; i++) {
|
||||
void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
|
||||
void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
|
||||
if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
|
||||
uea_write = &spr_write_generic;
|
||||
}
|
||||
|
|
@ -4680,7 +4675,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
|
|||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static void spr_write_mas73(void *opaque, int sprn, int gprn)
|
||||
static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv val = tcg_temp_new();
|
||||
tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
|
||||
|
|
@ -4690,7 +4685,7 @@ static void spr_write_mas73(void *opaque, int sprn, int gprn)
|
|||
tcg_temp_free(val);
|
||||
}
|
||||
|
||||
static void spr_read_mas73(void *opaque, int gprn, int sprn)
|
||||
static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
TCGv mas7 = tcg_temp_new();
|
||||
TCGv mas3 = tcg_temp_new();
|
||||
|
|
@ -7322,14 +7317,14 @@ enum BOOK3S_CPU_TYPE {
|
|||
BOOK3S_CPU_POWER8
|
||||
};
|
||||
|
||||
static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
|
||||
int sprn, int cause)
|
||||
static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
|
||||
int bit, int sprn, int cause)
|
||||
{
|
||||
TCGv_i32 t1 = tcg_const_i32(bit);
|
||||
TCGv_i32 t2 = tcg_const_i32(sprn);
|
||||
TCGv_i32 t3 = tcg_const_i32(cause);
|
||||
|
||||
gen_update_current_nip(opaque);
|
||||
gen_update_current_nip(ctx);
|
||||
gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
|
||||
|
||||
tcg_temp_free_i32(t3);
|
||||
|
|
@ -7337,14 +7332,14 @@ static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
|
|||
tcg_temp_free_i32(t1);
|
||||
}
|
||||
|
||||
static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit,
|
||||
int sprn, int cause)
|
||||
static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
|
||||
int bit, int sprn, int cause)
|
||||
{
|
||||
TCGv_i32 t1 = tcg_const_i32(bit);
|
||||
TCGv_i32 t2 = tcg_const_i32(sprn);
|
||||
TCGv_i32 t3 = tcg_const_i32(cause);
|
||||
|
||||
gen_update_current_nip(opaque);
|
||||
gen_update_current_nip(ctx);
|
||||
gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
|
||||
|
||||
tcg_temp_free_i32(t3);
|
||||
|
|
@ -7352,7 +7347,7 @@ static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit,
|
|||
tcg_temp_free_i32(t1);
|
||||
}
|
||||
|
||||
static void spr_read_prev_upper32(void *opaque, int gprn, int sprn)
|
||||
static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
TCGv spr_up = tcg_temp_new();
|
||||
TCGv spr = tcg_temp_new();
|
||||
|
|
@ -7365,7 +7360,7 @@ static void spr_read_prev_upper32(void *opaque, int gprn, int sprn)
|
|||
tcg_temp_free(spr_up);
|
||||
}
|
||||
|
||||
static void spr_write_prev_upper32(void *opaque, int sprn, int gprn)
|
||||
static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
TCGv spr = tcg_temp_new();
|
||||
|
||||
|
|
@ -7704,16 +7699,16 @@ static void gen_spr_power6_common(CPUPPCState *env)
|
|||
0x00000000);
|
||||
}
|
||||
|
||||
static void spr_read_tar(void *opaque, int gprn, int sprn)
|
||||
static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
|
||||
spr_read_generic(opaque, gprn, sprn);
|
||||
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
|
||||
spr_read_generic(ctx, gprn, sprn);
|
||||
}
|
||||
|
||||
static void spr_write_tar(void *opaque, int sprn, int gprn)
|
||||
static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
|
||||
spr_write_generic(opaque, sprn, gprn);
|
||||
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
|
||||
spr_write_generic(ctx, sprn, gprn);
|
||||
}
|
||||
|
||||
static void gen_spr_power8_tce_address_control(CPUPPCState *env)
|
||||
|
|
@ -7724,28 +7719,28 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
|
|||
0x00000000);
|
||||
}
|
||||
|
||||
static void spr_read_tm(void *opaque, int gprn, int sprn)
|
||||
static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
|
||||
spr_read_generic(opaque, gprn, sprn);
|
||||
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
|
||||
spr_read_generic(ctx, gprn, sprn);
|
||||
}
|
||||
|
||||
static void spr_write_tm(void *opaque, int sprn, int gprn)
|
||||
static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
|
||||
spr_write_generic(opaque, sprn, gprn);
|
||||
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
|
||||
spr_write_generic(ctx, sprn, gprn);
|
||||
}
|
||||
|
||||
static void spr_read_tm_upper32(void *opaque, int gprn, int sprn)
|
||||
static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
|
||||
spr_read_prev_upper32(opaque, gprn, sprn);
|
||||
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
|
||||
spr_read_prev_upper32(ctx, gprn, sprn);
|
||||
}
|
||||
|
||||
static void spr_write_tm_upper32(void *opaque, int sprn, int gprn)
|
||||
static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
|
||||
spr_write_prev_upper32(opaque, sprn, gprn);
|
||||
gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
|
||||
spr_write_prev_upper32(ctx, sprn, gprn);
|
||||
}
|
||||
|
||||
static void gen_spr_power8_tm(CPUPPCState *env)
|
||||
|
|
@ -7768,28 +7763,28 @@ static void gen_spr_power8_tm(CPUPPCState *env)
|
|||
0x00000000);
|
||||
}
|
||||
|
||||
static void spr_read_ebb(void *opaque, int gprn, int sprn)
|
||||
static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
|
||||
spr_read_generic(opaque, gprn, sprn);
|
||||
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
|
||||
spr_read_generic(ctx, gprn, sprn);
|
||||
}
|
||||
|
||||
static void spr_write_ebb(void *opaque, int sprn, int gprn)
|
||||
static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
|
||||
spr_write_generic(opaque, sprn, gprn);
|
||||
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
|
||||
spr_write_generic(ctx, sprn, gprn);
|
||||
}
|
||||
|
||||
static void spr_read_ebb_upper32(void *opaque, int gprn, int sprn)
|
||||
static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
|
||||
spr_read_prev_upper32(opaque, gprn, sprn);
|
||||
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
|
||||
spr_read_prev_upper32(ctx, gprn, sprn);
|
||||
}
|
||||
|
||||
static void spr_write_ebb_upper32(void *opaque, int sprn, int gprn)
|
||||
static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
|
||||
spr_write_prev_upper32(opaque, sprn, gprn);
|
||||
gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
|
||||
spr_write_prev_upper32(ctx, sprn, gprn);
|
||||
}
|
||||
|
||||
static void gen_spr_power8_ebb(CPUPPCState *env)
|
||||
|
|
|
|||
Loading…
Reference in New Issue