hw/ppc/ppc405_uc: Convert away from old_mmio
Convert the devices in ppc405_uc away from using the old_mmio MemoryRegion accessors: * opba's 32-bit and 16-bit accessors were just calling the 8-bit accessors and assembling a big-endian order number, which we can do by setting the .impl.max_access_size to 1 and the endianness to DEVICE_BIG_ENDIAN, and letting the core memory code do the assembly * ppc405_gpio's accessors were all just stubs * ppc4xx_gpt's 8-bit and 16-bit accessors were treating the access as invalid, which we can do by setting the .valid.min_access_size and .valid.max_access_size fields Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Peter Maydell
David Gibson
parent
878a460704
commit
69bd18f843
@ -283,7 +283,7 @@ struct ppc4xx_opba_t {
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uint8_t pr;
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};
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static uint32_t opba_readb (void *opaque, hwaddr addr)
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static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
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{
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ppc4xx_opba_t *opba;
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uint32_t ret;
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@ -307,8 +307,8 @@ static uint32_t opba_readb (void *opaque, hwaddr addr)
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return ret;
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}
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static void opba_writeb (void *opaque,
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hwaddr addr, uint32_t value)
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static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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ppc4xx_opba_t *opba;
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@ -328,61 +328,14 @@ static void opba_writeb (void *opaque,
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break;
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}
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}
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static uint32_t opba_readw (void *opaque, hwaddr addr)
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{
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uint32_t ret;
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#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = opba_readb(opaque, addr) << 8;
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ret |= opba_readb(opaque, addr + 1);
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return ret;
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}
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static void opba_writew (void *opaque,
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hwaddr addr, uint32_t value)
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{
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#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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opba_writeb(opaque, addr, value >> 8);
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opba_writeb(opaque, addr + 1, value);
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}
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static uint32_t opba_readl (void *opaque, hwaddr addr)
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{
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uint32_t ret;
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#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = opba_readb(opaque, addr) << 24;
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ret |= opba_readb(opaque, addr + 1) << 16;
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return ret;
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}
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static void opba_writel (void *opaque,
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hwaddr addr, uint32_t value)
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{
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#ifdef DEBUG_OPBA
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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opba_writeb(opaque, addr, value >> 24);
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opba_writeb(opaque, addr + 1, value >> 16);
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}
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static const MemoryRegionOps opba_ops = {
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.old_mmio = {
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.read = { opba_readb, opba_readw, opba_readl, },
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.write = { opba_writeb, opba_writew, opba_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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.read = opba_readb,
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.write = opba_writeb,
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.impl.min_access_size = 1,
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.impl.max_access_size = 1,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void ppc4xx_opba_reset (void *opaque)
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@ -750,65 +703,27 @@ struct ppc405_gpio_t {
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uint32_t isr1l;
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};
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static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
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static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
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{
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size);
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#endif
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return 0;
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}
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static void ppc405_gpio_writeb (void *opaque,
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hwaddr addr, uint32_t value)
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static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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}
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static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
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{
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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return 0;
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}
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static void ppc405_gpio_writew (void *opaque,
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hwaddr addr, uint32_t value)
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{
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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}
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static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
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{
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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return 0;
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}
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static void ppc405_gpio_writel (void *opaque,
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hwaddr addr, uint32_t value)
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{
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#ifdef DEBUG_GPIO
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n",
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__func__, addr, size, value);
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#endif
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}
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static const MemoryRegionOps ppc405_gpio_ops = {
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.old_mmio = {
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.read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
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.write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
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},
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.read = ppc405_gpio_read,
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.write = ppc405_gpio_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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@ -1017,44 +932,6 @@ struct ppc4xx_gpt_t {
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uint32_t mask[5];
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};
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static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
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{
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#ifdef DEBUG_GPT
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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/* XXX: generate a bus fault */
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return -1;
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}
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static void ppc4xx_gpt_writeb (void *opaque,
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hwaddr addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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/* XXX: generate a bus fault */
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}
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static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
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{
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#ifdef DEBUG_GPT
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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/* XXX: generate a bus fault */
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return -1;
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}
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static void ppc4xx_gpt_writew (void *opaque,
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hwaddr addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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/* XXX: generate a bus fault */
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}
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static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
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{
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/* XXX: TODO */
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@ -1107,7 +984,7 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
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/* XXX: TODO */
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}
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static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
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static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
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{
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ppc4xx_gpt_t *gpt;
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uint32_t ret;
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@ -1162,8 +1039,8 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
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return ret;
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}
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static void ppc4xx_gpt_writel (void *opaque,
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hwaddr addr, uint32_t value)
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static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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ppc4xx_gpt_t *gpt;
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int idx;
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@ -1225,10 +1102,10 @@ static void ppc4xx_gpt_writel (void *opaque,
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}
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static const MemoryRegionOps gpt_ops = {
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.old_mmio = {
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.read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
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.write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
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},
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.read = ppc4xx_gpt_read,
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.write = ppc4xx_gpt_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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