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target/arm: Use store_reg_from_load in thumb2 code 

This function already includes the test for an interworking write
to PC from a load.  Change the T32 LDM implementation to match the
A32 LDM implementation.

For LDM, the reordering of the tests does not change valid
behaviour because the only case that differs is has rn == 15,
which is UNPREDICTABLE.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:29:51 -07:00 committed by Peter Maydell
parent 500efcfcf0
commit 69be3e1376
1 changed files with 3 additions and 9 deletions
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12
target/arm/translate.c
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@ -9742,13 +9742,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* Load. */
tmp = tcg_temp_new_i32();
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
if (i == 15) {
gen_bx_excret(s, tmp);
} else if (i == rn) {
if (i == rn) {
loaded_var = tmp;
loaded_base = 1;
} else {
store_reg(s, i, tmp);
store_reg_from_load(s, i, tmp);
}
} else {
/* Store. */
@ -10889,11 +10887,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(addr);
goto illegal_op;
}
if (rs == 15) {
gen_bx_excret(s, tmp);
} else {
store_reg(s, rs, tmp);
}
store_reg_from_load(s, rs, tmp);
} else {
/* Store. */
tmp = load_reg(s, rs);