From 6a3ffda2ba4f3d4895c8d45d35feb61ddbd3a4f5 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:52:01 -0300 Subject: [PATCH] target/riscv: remove RISCV_FEATURE_EPMP RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-7-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 10 +++------- target/riscv/cpu.h | 1 - target/riscv/csr.c | 2 +- target/riscv/pmp.c | 4 ++-- 4 files changed, 6 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index aec7830c44..807a466f34 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_feature(env, RISCV_FEATURE_PMP); } - if (cpu->cfg.epmp) { - riscv_set_feature(env, RISCV_FEATURE_EPMP); - + if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available * on harts with PMP support */ - if (!cpu->cfg.pmp) { - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); - return; - } + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc62554e14..471e587729 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,7 +88,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, - RISCV_FEATURE_EPMP, }; /* Privileged specification version */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e220c4a5fd..951327022d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno) static RISCVException epmp(CPURISCVState *env, int csrno) { - if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 4bc4113531..aa4d1996e9 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) if (pmp_index < MAX_RISCV_PMPS) { bool locked = true; - if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (riscv_cpu_cfg(env)->epmp) { /* mseccfg.RLB is set */ if (MSECCFG_RLB_ISSET(env)) { locked = false; @@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, { bool ret; - if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (riscv_cpu_cfg(env)->epmp) { if (MSECCFG_MMWP_ISSET(env)) { /* * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set