* Fix "unused variable" warnings from Clang 15
* Allow building of guest-agent without emulators or tools * White space clean-ups * Fixes for typos in the documentation -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmNuI5YRHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbXfjRAAsUf7C77pVZj5VWpAVYSgHdYJ5WCfVQg3 Nd4Yixyx8b6yhgY1Vv9OL/uuY04AAWifQn0AUnNBJKrOKcuvU3mHlE/s1imw9CUf tsX2gE1GAczQqp5dLL2/+FCMZOC/acFkjmA9LAdOfG7eKzodRdsq/ZaIXd2+MmfM nG972Zw0/ZJqQs+DtjwNYvgtywEmRqunKIaCaSwtGHWvot081yw1iW3PvgrKulEr v9SQhAurD+ZxcJSeTn3c8L//KYVyCUGQ0K/1cbBcyhPi7xMQar8j7xuCk7xZiOMW fvhCOSnjbntsf+xnE2VDlakKQvoY6r30Tl0dzSoH79uzGe+ZTPC+L6ly3tzJ0Vo6 aslppY+8oYxLbJRX1Im8X0rxK6OqcVjjEXu3fVn8/C1WftIltuy3va2LZNZfQ8Bf +Yte3swzvFzgQE19c0HkgMd4uvfqGIkyprs1n2RjzZaI7cnQ4Ati/wQsOKCUrqrY VYsy3J1IypM7DO/cZ/JpdDV3PPTWv8JI8H2Agn2VhvY86N9ETn71RAj6UYqufW3W H3lMv7L6rU8c1tfcjbr0Xf811EwHekkIjyGt0aJ8MacJNkSc1A4pe+UUGVxNefue W0kT2htHQL1Q9JWjbKQuqT/rYrKUfqRDnd809YAzEVO7jpabS8g/hN3wBiaeZDgK LqLnITUBhRU= =H8p7 -----END PGP SIGNATURE----- Merge tag 'pull-request-2022-11-11' of https://gitlab.com/thuth/qemu into staging * Fix "unused variable" warnings from Clang 15 * Allow building of guest-agent without emulators or tools * White space clean-ups * Fixes for typos in the documentation # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmNuI5YRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbXfjRAAsUf7C77pVZj5VWpAVYSgHdYJ5WCfVQg3 # Nd4Yixyx8b6yhgY1Vv9OL/uuY04AAWifQn0AUnNBJKrOKcuvU3mHlE/s1imw9CUf # tsX2gE1GAczQqp5dLL2/+FCMZOC/acFkjmA9LAdOfG7eKzodRdsq/ZaIXd2+MmfM # nG972Zw0/ZJqQs+DtjwNYvgtywEmRqunKIaCaSwtGHWvot081yw1iW3PvgrKulEr # v9SQhAurD+ZxcJSeTn3c8L//KYVyCUGQ0K/1cbBcyhPi7xMQar8j7xuCk7xZiOMW # fvhCOSnjbntsf+xnE2VDlakKQvoY6r30Tl0dzSoH79uzGe+ZTPC+L6ly3tzJ0Vo6 # aslppY+8oYxLbJRX1Im8X0rxK6OqcVjjEXu3fVn8/C1WftIltuy3va2LZNZfQ8Bf # +Yte3swzvFzgQE19c0HkgMd4uvfqGIkyprs1n2RjzZaI7cnQ4Ati/wQsOKCUrqrY # VYsy3J1IypM7DO/cZ/JpdDV3PPTWv8JI8H2Agn2VhvY86N9ETn71RAj6UYqufW3W # H3lMv7L6rU8c1tfcjbr0Xf811EwHekkIjyGt0aJ8MacJNkSc1A4pe+UUGVxNefue # W0kT2htHQL1Q9JWjbKQuqT/rYrKUfqRDnd809YAzEVO7jpabS8g/hN3wBiaeZDgK # LqLnITUBhRU= # =H8p7 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 11 Nov 2022 05:27:34 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-11-11' of https://gitlab.com/thuth/qemu: Fix several typos in documentation (found by codespell) net: Replace TAB indentations with spaces qga: Allow building of the guest agent without system emulators or tools libdecnumber/dpd/decimal64: Fix compiler warning from Clang 15 host-libusb: Remove unused variable qemu-img: remove unused variable tulip: Remove unused variable rtl8139: Remove unused variable Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
6a4cff8e1a
@ -132,7 +132,7 @@ Under ``tests/avocado/`` as the root we have:
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(a) They are python2.7 based scripts and not python 3 scripts.
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(b) They are run from within the bios bits VM and is not subjected to QEMU
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build/test python script maintainance and dependency resolutions.
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build/test python script maintenance and dependency resolutions.
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(c) They need not be loaded by avocado framework when running tests.
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@ -169,8 +169,9 @@ and with bitrate switch::
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cangen can0 -b
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The test can be run viceversa, generate messages in the guest system and capture them
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in the host one and much more combinations.
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The test can also be run the other way around, generating messages in the
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guest system and capturing them in the host system. Other combinations are
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also possible.
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Links to other resources
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------------------------
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@ -34,156 +34,156 @@
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/* CAN_Frame_format memory map */
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enum ctu_can_fd_can_frame_format {
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CTU_CAN_FD_FRAME_FORM_W = 0x0,
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CTU_CAN_FD_IDENTIFIER_W = 0x4,
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CTU_CAN_FD_TIMESTAMP_L_W = 0x8,
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CTU_CAN_FD_TIMESTAMP_U_W = 0xc,
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CTU_CAN_FD_DATA_1_4_W = 0x10,
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CTU_CAN_FD_DATA_5_8_W = 0x14,
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CTU_CAN_FD_DATA_61_64_W = 0x4c,
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CTU_CAN_FD_FRAME_FORM_W = 0x0,
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CTU_CAN_FD_IDENTIFIER_W = 0x4,
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CTU_CAN_FD_TIMESTAMP_L_W = 0x8,
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CTU_CAN_FD_TIMESTAMP_U_W = 0xc,
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CTU_CAN_FD_DATA_1_4_W = 0x10,
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CTU_CAN_FD_DATA_5_8_W = 0x14,
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CTU_CAN_FD_DATA_61_64_W = 0x4c,
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};
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/* Register descriptions: */
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union ctu_can_fd_frame_form_w {
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uint32_t u32;
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struct ctu_can_fd_frame_form_w_s {
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uint32_t u32;
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struct ctu_can_fd_frame_form_w_s {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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/* FRAME_FORM_W */
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uint32_t dlc : 4;
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uint32_t reserved_4 : 1;
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uint32_t rtr : 1;
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uint32_t ide : 1;
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uint32_t fdf : 1;
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uint32_t reserved_8 : 1;
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uint32_t brs : 1;
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uint32_t esi_rsv : 1;
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uint32_t rwcnt : 5;
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uint32_t reserved_31_16 : 16;
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uint32_t dlc : 4;
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uint32_t reserved_4 : 1;
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uint32_t rtr : 1;
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uint32_t ide : 1;
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uint32_t fdf : 1;
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uint32_t reserved_8 : 1;
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uint32_t brs : 1;
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uint32_t esi_rsv : 1;
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uint32_t rwcnt : 5;
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uint32_t reserved_31_16 : 16;
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#else
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uint32_t reserved_31_16 : 16;
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uint32_t rwcnt : 5;
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uint32_t esi_rsv : 1;
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uint32_t brs : 1;
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uint32_t reserved_8 : 1;
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uint32_t fdf : 1;
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uint32_t ide : 1;
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uint32_t rtr : 1;
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uint32_t reserved_4 : 1;
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uint32_t dlc : 4;
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uint32_t reserved_31_16 : 16;
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uint32_t rwcnt : 5;
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uint32_t esi_rsv : 1;
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uint32_t brs : 1;
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uint32_t reserved_8 : 1;
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uint32_t fdf : 1;
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uint32_t ide : 1;
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uint32_t rtr : 1;
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uint32_t reserved_4 : 1;
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uint32_t dlc : 4;
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#endif
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} s;
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} s;
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};
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enum ctu_can_fd_frame_form_w_rtr {
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NO_RTR_FRAME = 0x0,
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RTR_FRAME = 0x1,
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NO_RTR_FRAME = 0x0,
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RTR_FRAME = 0x1,
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};
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enum ctu_can_fd_frame_form_w_ide {
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BASE = 0x0,
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EXTENDED = 0x1,
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BASE = 0x0,
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EXTENDED = 0x1,
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};
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enum ctu_can_fd_frame_form_w_fdf {
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NORMAL_CAN = 0x0,
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FD_CAN = 0x1,
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NORMAL_CAN = 0x0,
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FD_CAN = 0x1,
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};
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enum ctu_can_fd_frame_form_w_brs {
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BR_NO_SHIFT = 0x0,
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BR_SHIFT = 0x1,
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BR_NO_SHIFT = 0x0,
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BR_SHIFT = 0x1,
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};
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enum ctu_can_fd_frame_form_w_esi_rsv {
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ESI_ERR_ACTIVE = 0x0,
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ESI_ERR_PASIVE = 0x1,
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ESI_ERR_ACTIVE = 0x0,
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ESI_ERR_PASIVE = 0x1,
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};
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union ctu_can_fd_identifier_w {
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uint32_t u32;
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struct ctu_can_fd_identifier_w_s {
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uint32_t u32;
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struct ctu_can_fd_identifier_w_s {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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/* IDENTIFIER_W */
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uint32_t identifier_ext : 18;
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uint32_t identifier_base : 11;
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uint32_t reserved_31_29 : 3;
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uint32_t identifier_ext : 18;
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uint32_t identifier_base : 11;
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uint32_t reserved_31_29 : 3;
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#else
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uint32_t reserved_31_29 : 3;
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uint32_t identifier_base : 11;
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uint32_t identifier_ext : 18;
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uint32_t reserved_31_29 : 3;
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uint32_t identifier_base : 11;
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uint32_t identifier_ext : 18;
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#endif
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} s;
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} s;
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};
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union ctu_can_fd_timestamp_l_w {
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uint32_t u32;
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struct ctu_can_fd_timestamp_l_w_s {
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uint32_t u32;
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struct ctu_can_fd_timestamp_l_w_s {
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/* TIMESTAMP_L_W */
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uint32_t time_stamp_31_0 : 32;
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} s;
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uint32_t time_stamp_31_0 : 32;
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} s;
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};
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union ctu_can_fd_timestamp_u_w {
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uint32_t u32;
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struct ctu_can_fd_timestamp_u_w_s {
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uint32_t u32;
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struct ctu_can_fd_timestamp_u_w_s {
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/* TIMESTAMP_U_W */
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uint32_t timestamp_l_w : 32;
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} s;
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uint32_t timestamp_l_w : 32;
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} s;
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};
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union ctu_can_fd_data_1_4_w {
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uint32_t u32;
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struct ctu_can_fd_data_1_4_w_s {
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uint32_t u32;
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struct ctu_can_fd_data_1_4_w_s {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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/* DATA_1_4_W */
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uint32_t data_1 : 8;
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uint32_t data_2 : 8;
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uint32_t data_3 : 8;
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uint32_t data_4 : 8;
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uint32_t data_1 : 8;
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uint32_t data_2 : 8;
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uint32_t data_3 : 8;
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uint32_t data_4 : 8;
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#else
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uint32_t data_4 : 8;
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uint32_t data_3 : 8;
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uint32_t data_2 : 8;
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uint32_t data_1 : 8;
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uint32_t data_4 : 8;
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uint32_t data_3 : 8;
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uint32_t data_2 : 8;
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uint32_t data_1 : 8;
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#endif
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} s;
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} s;
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};
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union ctu_can_fd_data_5_8_w {
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uint32_t u32;
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struct ctu_can_fd_data_5_8_w_s {
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uint32_t u32;
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struct ctu_can_fd_data_5_8_w_s {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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/* DATA_5_8_W */
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uint32_t data_5 : 8;
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uint32_t data_6 : 8;
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uint32_t data_7 : 8;
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uint32_t data_8 : 8;
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uint32_t data_5 : 8;
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uint32_t data_6 : 8;
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uint32_t data_7 : 8;
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uint32_t data_8 : 8;
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#else
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uint32_t data_8 : 8;
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uint32_t data_7 : 8;
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uint32_t data_6 : 8;
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uint32_t data_5 : 8;
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uint32_t data_8 : 8;
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uint32_t data_7 : 8;
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uint32_t data_6 : 8;
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uint32_t data_5 : 8;
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#endif
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} s;
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} s;
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};
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union ctu_can_fd_data_61_64_w {
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uint32_t u32;
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struct ctu_can_fd_data_61_64_w_s {
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uint32_t u32;
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struct ctu_can_fd_data_61_64_w_s {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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/* DATA_61_64_W */
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uint32_t data_61 : 8;
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uint32_t data_62 : 8;
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uint32_t data_63 : 8;
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uint32_t data_64 : 8;
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uint32_t data_61 : 8;
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uint32_t data_62 : 8;
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uint32_t data_63 : 8;
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uint32_t data_64 : 8;
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#else
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uint32_t data_64 : 8;
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uint32_t data_63 : 8;
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uint32_t data_62 : 8;
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uint32_t data_61 : 8;
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uint32_t data_64 : 8;
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uint32_t data_63 : 8;
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uint32_t data_62 : 8;
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uint32_t data_61 : 8;
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#endif
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} s;
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} s;
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};
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#endif
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File diff suppressed because it is too large
Load Diff
@ -552,21 +552,21 @@
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#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
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/* PHY Status Register */
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#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
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#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
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#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
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#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
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#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
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#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
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#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
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#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
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#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
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#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
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#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
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#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
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#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
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#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
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#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
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#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
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#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
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#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
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#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
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#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
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#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
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#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
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#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
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#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
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#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
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#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
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#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
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#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
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#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
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#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
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/* PHY Link Partner Ability Register */
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#define MII_LPAR_LPACK 0x4000 /* Acked by link partner */
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@ -313,10 +313,10 @@ static void mcf_fec_reset(DeviceState *dev)
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s->rfsr = 0x500;
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}
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#define MMFR_WRITE_OP (1 << 28)
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#define MMFR_READ_OP (2 << 28)
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#define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
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#define MMFR_REGNUM(v) (((v) >> 18) & 0x1f)
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#define MMFR_WRITE_OP (1 << 28)
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#define MMFR_READ_OP (2 << 28)
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#define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
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#define MMFR_REGNUM(v) (((v) >> 18) & 0x1f)
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static uint64_t mcf_fec_read_mdio(mcf_fec_state *s)
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{
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138
hw/net/ne2000.c
138
hw/net/ne2000.c
@ -36,89 +36,89 @@
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#define MAX_ETH_FRAME_SIZE 1514
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#define E8390_CMD 0x00 /* The command register (for all pages) */
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#define E8390_CMD 0x00 /* The command register (for all pages) */
|
||||
/* Page 0 register offsets. */
|
||||
#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
|
||||
#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
|
||||
#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
|
||||
#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
|
||||
#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
|
||||
#define EN0_TSR 0x04 /* Transmit status reg RD */
|
||||
#define EN0_TPSR 0x04 /* Transmit starting page WR */
|
||||
#define EN0_NCR 0x05 /* Number of collision reg RD */
|
||||
#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
|
||||
#define EN0_FIFO 0x06 /* FIFO RD */
|
||||
#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
|
||||
#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
|
||||
#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
|
||||
#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
|
||||
#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
|
||||
#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
|
||||
#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
|
||||
#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
|
||||
#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
|
||||
#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
|
||||
#define EN0_RSR 0x0c /* rx status reg RD */
|
||||
#define EN0_RXCR 0x0c /* RX configuration reg WR */
|
||||
#define EN0_TXCR 0x0d /* TX configuration reg WR */
|
||||
#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
|
||||
#define EN0_DCFG 0x0e /* Data configuration reg WR */
|
||||
#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
|
||||
#define EN0_IMR 0x0f /* Interrupt mask reg WR */
|
||||
#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
|
||||
#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
|
||||
#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
|
||||
#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
|
||||
#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
|
||||
#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
|
||||
#define EN0_TSR 0x04 /* Transmit status reg RD */
|
||||
#define EN0_TPSR 0x04 /* Transmit starting page WR */
|
||||
#define EN0_NCR 0x05 /* Number of collision reg RD */
|
||||
#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
|
||||
#define EN0_FIFO 0x06 /* FIFO RD */
|
||||
#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
|
||||
#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
|
||||
#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
|
||||
#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
|
||||
#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
|
||||
#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
|
||||
#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
|
||||
#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
|
||||
#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
|
||||
#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
|
||||
#define EN0_RSR 0x0c /* rx status reg RD */
|
||||
#define EN0_RXCR 0x0c /* RX configuration reg WR */
|
||||
#define EN0_TXCR 0x0d /* TX configuration reg WR */
|
||||
#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
|
||||
#define EN0_DCFG 0x0e /* Data configuration reg WR */
|
||||
#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
|
||||
#define EN0_IMR 0x0f /* Interrupt mask reg WR */
|
||||
#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
|
||||
|
||||
#define EN1_PHYS 0x11
|
||||
#define EN1_CURPAG 0x17
|
||||
#define EN1_MULT 0x18
|
||||
|
||||
#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
|
||||
#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
|
||||
#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
|
||||
#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
|
||||
|
||||
#define EN3_CONFIG0 0x33
|
||||
#define EN3_CONFIG1 0x34
|
||||
#define EN3_CONFIG2 0x35
|
||||
#define EN3_CONFIG3 0x36
|
||||
#define EN3_CONFIG0 0x33
|
||||
#define EN3_CONFIG1 0x34
|
||||
#define EN3_CONFIG2 0x35
|
||||
#define EN3_CONFIG3 0x36
|
||||
|
||||
/* Register accessed at EN_CMD, the 8390 base addr. */
|
||||
#define E8390_STOP 0x01 /* Stop and reset the chip */
|
||||
#define E8390_START 0x02 /* Start the chip, clear reset */
|
||||
#define E8390_TRANS 0x04 /* Transmit a frame */
|
||||
#define E8390_RREAD 0x08 /* Remote read */
|
||||
#define E8390_RWRITE 0x10 /* Remote write */
|
||||
#define E8390_NODMA 0x20 /* Remote DMA */
|
||||
#define E8390_PAGE0 0x00 /* Select page chip registers */
|
||||
#define E8390_PAGE1 0x40 /* using the two high-order bits */
|
||||
#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
|
||||
#define E8390_STOP 0x01 /* Stop and reset the chip */
|
||||
#define E8390_START 0x02 /* Start the chip, clear reset */
|
||||
#define E8390_TRANS 0x04 /* Transmit a frame */
|
||||
#define E8390_RREAD 0x08 /* Remote read */
|
||||
#define E8390_RWRITE 0x10 /* Remote write */
|
||||
#define E8390_NODMA 0x20 /* Remote DMA */
|
||||
#define E8390_PAGE0 0x00 /* Select page chip registers */
|
||||
#define E8390_PAGE1 0x40 /* using the two high-order bits */
|
||||
#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
|
||||
|
||||
/* Bits in EN0_ISR - Interrupt status register */
|
||||
#define ENISR_RX 0x01 /* Receiver, no error */
|
||||
#define ENISR_TX 0x02 /* Transmitter, no error */
|
||||
#define ENISR_RX_ERR 0x04 /* Receiver, with error */
|
||||
#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
|
||||
#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
|
||||
#define ENISR_COUNTERS 0x20 /* Counters need emptying */
|
||||
#define ENISR_RDC 0x40 /* remote dma complete */
|
||||
#define ENISR_RESET 0x80 /* Reset completed */
|
||||
#define ENISR_ALL 0x3f /* Interrupts we will enable */
|
||||
#define ENISR_RX 0x01 /* Receiver, no error */
|
||||
#define ENISR_TX 0x02 /* Transmitter, no error */
|
||||
#define ENISR_RX_ERR 0x04 /* Receiver, with error */
|
||||
#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
|
||||
#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
|
||||
#define ENISR_COUNTERS 0x20 /* Counters need emptying */
|
||||
#define ENISR_RDC 0x40 /* remote dma complete */
|
||||
#define ENISR_RESET 0x80 /* Reset completed */
|
||||
#define ENISR_ALL 0x3f /* Interrupts we will enable */
|
||||
|
||||
/* Bits in received packet status byte and EN0_RSR*/
|
||||
#define ENRSR_RXOK 0x01 /* Received a good packet */
|
||||
#define ENRSR_CRC 0x02 /* CRC error */
|
||||
#define ENRSR_FAE 0x04 /* frame alignment error */
|
||||
#define ENRSR_FO 0x08 /* FIFO overrun */
|
||||
#define ENRSR_MPA 0x10 /* missed pkt */
|
||||
#define ENRSR_PHY 0x20 /* physical/multicast address */
|
||||
#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
|
||||
#define ENRSR_DEF 0x80 /* deferring */
|
||||
#define ENRSR_RXOK 0x01 /* Received a good packet */
|
||||
#define ENRSR_CRC 0x02 /* CRC error */
|
||||
#define ENRSR_FAE 0x04 /* frame alignment error */
|
||||
#define ENRSR_FO 0x08 /* FIFO overrun */
|
||||
#define ENRSR_MPA 0x10 /* missed pkt */
|
||||
#define ENRSR_PHY 0x20 /* physical/multicast address */
|
||||
#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
|
||||
#define ENRSR_DEF 0x80 /* deferring */
|
||||
|
||||
/* Transmitted packet status, EN0_TSR. */
|
||||
#define ENTSR_PTX 0x01 /* Packet transmitted without error */
|
||||
#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
|
||||
#define ENTSR_COL 0x04 /* The transmit collided at least once. */
|
||||
#define ENTSR_PTX 0x01 /* Packet transmitted without error */
|
||||
#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
|
||||
#define ENTSR_COL 0x04 /* The transmit collided at least once. */
|
||||
#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
|
||||
#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
|
||||
#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
|
||||
#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
|
||||
#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
|
||||
#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
|
||||
#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
|
||||
|
||||
void ne2000_reset(NE2000State *s)
|
||||
@ -425,13 +425,13 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
|
||||
ret = 0x43;
|
||||
break;
|
||||
case EN3_CONFIG0:
|
||||
ret = 0; /* 10baseT media */
|
||||
ret = 0; /* 10baseT media */
|
||||
break;
|
||||
case EN3_CONFIG2:
|
||||
ret = 0x40; /* 10baseT active */
|
||||
ret = 0x40; /* 10baseT active */
|
||||
break;
|
||||
case EN3_CONFIG3:
|
||||
ret = 0x40; /* Full duplex */
|
||||
ret = 0x40; /* Full duplex */
|
||||
break;
|
||||
default:
|
||||
ret = 0x00;
|
||||
|
||||
136
hw/net/pcnet.c
136
hw/net/pcnet.c
@ -370,7 +370,7 @@ static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
|
||||
uint32_t rbadr;
|
||||
int16_t buf_length;
|
||||
int16_t msg_length;
|
||||
} rda;
|
||||
} rda;
|
||||
s->phys_mem_read(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
|
||||
rmd->rbadr = le32_to_cpu(rda.rbadr) & 0xffffff;
|
||||
rmd->buf_length = le16_to_cpu(rda.buf_length);
|
||||
@ -524,77 +524,77 @@ static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
|
||||
be16_to_cpu(hdr->ether_type)); \
|
||||
} while (0)
|
||||
|
||||
#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
|
||||
#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
|
||||
|
||||
/* generated using the AUTODIN II polynomial
|
||||
* x^32 + x^26 + x^23 + x^22 + x^16 +
|
||||
* x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
|
||||
* x^32 + x^26 + x^23 + x^22 + x^16 +
|
||||
* x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
|
||||
*/
|
||||
static const uint32_t crctab[256] = {
|
||||
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
|
||||
0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
|
||||
0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
|
||||
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
|
||||
0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
|
||||
0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
|
||||
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
|
||||
0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
|
||||
0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
|
||||
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
|
||||
0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
|
||||
0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
|
||||
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
|
||||
0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
|
||||
0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
|
||||
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
|
||||
0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
|
||||
0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
|
||||
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
|
||||
0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
|
||||
0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
|
||||
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
|
||||
0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
|
||||
0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
|
||||
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
|
||||
0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
|
||||
0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
|
||||
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
|
||||
0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
|
||||
0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
|
||||
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
|
||||
0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
|
||||
0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
|
||||
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
|
||||
0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
|
||||
0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
|
||||
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
|
||||
0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
|
||||
0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
|
||||
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
|
||||
0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
|
||||
0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
|
||||
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
|
||||
0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
|
||||
0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
|
||||
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
|
||||
0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
|
||||
0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
|
||||
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
|
||||
0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
|
||||
0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
|
||||
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
|
||||
0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
|
||||
0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
|
||||
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
|
||||
0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
|
||||
0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
|
||||
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
|
||||
0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
|
||||
0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
|
||||
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
|
||||
0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
|
||||
0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
|
||||
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
|
||||
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
|
||||
0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
|
||||
0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
|
||||
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
|
||||
0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
|
||||
0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
|
||||
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
|
||||
0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
|
||||
0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
|
||||
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
|
||||
0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
|
||||
0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
|
||||
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
|
||||
0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
|
||||
0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
|
||||
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
|
||||
0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
|
||||
0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
|
||||
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
|
||||
0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
|
||||
0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
|
||||
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
|
||||
0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
|
||||
0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
|
||||
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
|
||||
0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
|
||||
0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
|
||||
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
|
||||
0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
|
||||
0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
|
||||
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
|
||||
0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
|
||||
0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
|
||||
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
|
||||
0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
|
||||
0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
|
||||
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
|
||||
0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
|
||||
0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
|
||||
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
|
||||
0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
|
||||
0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
|
||||
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
|
||||
0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
|
||||
0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
|
||||
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
|
||||
0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
|
||||
0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
|
||||
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
|
||||
0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
|
||||
0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
|
||||
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
|
||||
0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
|
||||
0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
|
||||
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
|
||||
0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
|
||||
0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
|
||||
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
|
||||
0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
|
||||
0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
|
||||
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
|
||||
0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
|
||||
0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
|
||||
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
|
||||
};
|
||||
|
||||
static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)
|
||||
|
||||
@ -4,8 +4,8 @@
|
||||
#define PCNET_IOPORT_SIZE 0x20
|
||||
#define PCNET_PNPMMIO_SIZE 0x20
|
||||
|
||||
#define PCNET_LOOPTEST_CRC 1
|
||||
#define PCNET_LOOPTEST_NOCRC 2
|
||||
#define PCNET_LOOPTEST_CRC 1
|
||||
#define PCNET_LOOPTEST_NOCRC 2
|
||||
|
||||
#include "exec/memory.h"
|
||||
#include "hw/irq.h"
|
||||
|
||||
@ -2156,7 +2156,6 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
|
||||
ip_data_len, saved_size - ETH_HLEN, large_send_mss);
|
||||
|
||||
int tcp_send_offset = 0;
|
||||
int send_count = 0;
|
||||
|
||||
/* maximum IP header length is 60 bytes */
|
||||
uint8_t saved_ip_header[60];
|
||||
@ -2261,7 +2260,6 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
|
||||
/* add transferred count to TCP sequence number */
|
||||
stl_be_p(&p_tcp_hdr->th_seq,
|
||||
chunk_size + ldl_be_p(&p_tcp_hdr->th_seq));
|
||||
++send_count;
|
||||
}
|
||||
|
||||
/* Stop sending this frame */
|
||||
|
||||
@ -870,11 +870,10 @@ static const MemoryRegionOps tulip_ops = {
|
||||
|
||||
static void tulip_idblock_crc(TULIPState *s, uint16_t *srom)
|
||||
{
|
||||
int word, n;
|
||||
int word;
|
||||
int bit;
|
||||
unsigned char bitval, crc;
|
||||
const int len = 9;
|
||||
n = 0;
|
||||
crc = -1;
|
||||
|
||||
for (word = 0; word < len; word++) {
|
||||
@ -887,7 +886,6 @@ static void tulip_idblock_crc(TULIPState *s, uint16_t *srom)
|
||||
srom[len - 1] = (srom[len - 1] & 0xff00) | (unsigned short)crc;
|
||||
break;
|
||||
}
|
||||
n++;
|
||||
bitval = ((srom[word] >> bit) & 1) ^ ((crc >> 7) & 1);
|
||||
crc = crc << 1;
|
||||
if (bitval == 1) {
|
||||
|
||||
@ -515,7 +515,7 @@ static void do_dma_pdma_cb(ESPState *s)
|
||||
} else {
|
||||
/*
|
||||
* Extra message out bytes received: update cmdfifo_cdb_offset
|
||||
* and then switch to commmand phase
|
||||
* and then switch to command phase
|
||||
*/
|
||||
s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
|
||||
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
|
||||
@ -627,7 +627,7 @@ static void esp_do_dma(ESPState *s)
|
||||
} else {
|
||||
/*
|
||||
* Extra message out bytes received: update cmdfifo_cdb_offset
|
||||
* and then switch to commmand phase
|
||||
* and then switch to command phase
|
||||
*/
|
||||
s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
|
||||
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
|
||||
@ -738,7 +738,7 @@ static void esp_do_nodma(ESPState *s)
|
||||
} else {
|
||||
/*
|
||||
* Extra message out bytes received: update cmdfifo_cdb_offset
|
||||
* and then switch to commmand phase
|
||||
* and then switch to command phase
|
||||
*/
|
||||
s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
|
||||
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
|
||||
|
||||
@ -1837,7 +1837,6 @@ static void usb_host_auto_check(void *unused)
|
||||
struct USBAutoFilter *f;
|
||||
libusb_device **devs = NULL;
|
||||
struct libusb_device_descriptor ddesc;
|
||||
int unconnected = 0;
|
||||
int i, n;
|
||||
|
||||
if (usb_host_init() != 0) {
|
||||
@ -1897,9 +1896,6 @@ static void usb_host_auto_check(void *unused)
|
||||
libusb_free_device_list(devs, 1);
|
||||
|
||||
QTAILQ_FOREACH(s, &hostdevs, next) {
|
||||
if (s->dh == NULL) {
|
||||
unconnected++;
|
||||
}
|
||||
if (s->seen == 0) {
|
||||
if (s->dh) {
|
||||
usb_host_close(s);
|
||||
@ -1908,17 +1904,6 @@ static void usb_host_auto_check(void *unused)
|
||||
}
|
||||
s->seen = 0;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (unconnected == 0) {
|
||||
/* nothing to watch */
|
||||
if (usb_auto_timer) {
|
||||
timer_del(usb_auto_timer);
|
||||
trace_usb_host_auto_scan_disabled();
|
||||
}
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
if (!usb_vmstate) {
|
||||
|
||||
@ -561,7 +561,7 @@ typedef void (*ReplayRamDiscard)(MemoryRegionSection *section, void *opaque);
|
||||
* A #RamDiscardManager coordinates which parts of specific RAM #MemoryRegion
|
||||
* regions are currently populated to be used/accessed by the VM, notifying
|
||||
* after parts were discarded (freeing up memory) and before parts will be
|
||||
* populated (consuming memory), to be used/acessed by the VM.
|
||||
* populated (consuming memory), to be used/accessed by the VM.
|
||||
*
|
||||
* A #RamDiscardManager can only be set for a RAM #MemoryRegion while the
|
||||
* #MemoryRegion isn't mapped yet; it cannot change while the #MemoryRegion is
|
||||
@ -585,7 +585,7 @@ typedef void (*ReplayRamDiscard)(MemoryRegionSection *section, void *opaque);
|
||||
* Listeners are called in multiples of the minimum granularity (unless it
|
||||
* would exceed the registered range) and changes are aligned to the minimum
|
||||
* granularity within the #MemoryRegion. Listeners have to prepare for memory
|
||||
* becomming discarded in a different granularity than it was populated and the
|
||||
* becoming discarded in a different granularity than it was populated and the
|
||||
* other way around.
|
||||
*/
|
||||
struct RamDiscardManagerClass {
|
||||
@ -1247,7 +1247,7 @@ void memory_region_init_ram_flags_nomigrate(MemoryRegion *mr,
|
||||
Error **errp);
|
||||
|
||||
/**
|
||||
* memory_region_init_resizeable_ram: Initialize memory region with resizeable
|
||||
* memory_region_init_resizeable_ram: Initialize memory region with resizable
|
||||
* RAM. Accesses into the region will
|
||||
* modify memory directly. Only an initial
|
||||
* portion of this RAM is actually used.
|
||||
|
||||
@ -617,7 +617,6 @@ static const uInt multies[]={131073, 26215, 5243, 1049, 210};
|
||||
#endif
|
||||
void decDigitsToDPD(const decNumber *dn, uInt *targ, Int shift) {
|
||||
Int cut; /* work */
|
||||
Int n; /* output bunch counter */
|
||||
Int digits=dn->digits; /* digit countdown */
|
||||
uInt dpd; /* densely packed decimal value */
|
||||
uInt bin; /* binary value 0-999 */
|
||||
@ -676,7 +675,7 @@ void decDigitsToDPD(const decNumber *dn, uInt *targ, Int shift) {
|
||||
bin=0; /* [keep compiler quiet] */
|
||||
#endif
|
||||
|
||||
for(n=0; digits>0; n++) { /* each output bunch */
|
||||
while (digits > 0) { /* each output bunch */
|
||||
#if DECDPUN==3 /* fast path, 3-at-a-time */
|
||||
bin=*inu; /* 3 digits ready for convert */
|
||||
digits-=3; /* [may go negative] */
|
||||
|
||||
@ -45,10 +45,10 @@
|
||||
#define IFF_DETACH_QUEUE 0x0400
|
||||
|
||||
/* Features for GSO (TUNSETOFFLOAD). */
|
||||
#define TUN_F_CSUM 0x01 /* You can hand me unchecksummed packets. */
|
||||
#define TUN_F_TSO4 0x02 /* I can handle TSO for IPv4 packets */
|
||||
#define TUN_F_TSO6 0x04 /* I can handle TSO for IPv6 packets */
|
||||
#define TUN_F_TSO_ECN 0x08 /* I can handle TSO with ECN bits. */
|
||||
#define TUN_F_UFO 0x10 /* I can handle UFO packets */
|
||||
#define TUN_F_CSUM 0x01 /* You can hand me unchecksummed packets. */
|
||||
#define TUN_F_TSO4 0x02 /* I can handle TSO for IPv4 packets */
|
||||
#define TUN_F_TSO6 0x04 /* I can handle TSO for IPv6 packets */
|
||||
#define TUN_F_TSO_ECN 0x08 /* I can handle TSO with ECN bits. */
|
||||
#define TUN_F_UFO 0x10 /* I can handle UFO packets */
|
||||
|
||||
#endif /* QEMU_TAP_LINUX_H */
|
||||
|
||||
@ -13,7 +13,7 @@ util_ss.add(files(
|
||||
if have_system
|
||||
util_ss.add(files('qapi-type-helpers.c'))
|
||||
endif
|
||||
if have_system or have_tools
|
||||
if have_system or have_tools or have_ga
|
||||
util_ss.add(files(
|
||||
'qmp-dispatch.c',
|
||||
'qmp-event.c',
|
||||
|
||||
@ -321,7 +321,7 @@
|
||||
# },
|
||||
# "backend-features": {
|
||||
# "dev-features": [
|
||||
# "VHOST_USER_F_PROTOCOL_FEATURES: Vhost-user protocol features negotation supported",
|
||||
# "VHOST_USER_F_PROTOCOL_FEATURES: Vhost-user protocol features negotiation supported",
|
||||
# "VIRTIO_NET_F_GSO: Handling GSO-type packets supported",
|
||||
# "VIRTIO_NET_F_CTRL_MAC_ADDR: MAC address set through control channel",
|
||||
# "VIRTIO_NET_F_GUEST_ANNOUNCE: Driver sending gratuitous packets supported",
|
||||
@ -394,7 +394,7 @@
|
||||
# },
|
||||
# "host-features": {
|
||||
# "dev-features": [
|
||||
# "VHOST_USER_F_PROTOCOL_FEATURES: Vhost-user protocol features negotation supported",
|
||||
# "VHOST_USER_F_PROTOCOL_FEATURES: Vhost-user protocol features negotiation supported",
|
||||
# "VIRTIO_NET_F_GSO: Handling GSO-type packets supported",
|
||||
# "VIRTIO_NET_F_CTRL_MAC_ADDR: MAC address set through control channel",
|
||||
# "VIRTIO_NET_F_GUEST_ANNOUNCE: Driver sending gratuitous packets supported",
|
||||
|
||||
@ -4922,7 +4922,7 @@ static int img_dd(int argc, char **argv)
|
||||
const char *out_fmt = "raw";
|
||||
const char *fmt = NULL;
|
||||
int64_t size = 0;
|
||||
int64_t block_count = 0, out_pos, in_pos;
|
||||
int64_t out_pos, in_pos;
|
||||
bool force_share = false;
|
||||
struct DdInfo dd = {
|
||||
.flags = 0,
|
||||
@ -5122,7 +5122,7 @@ static int img_dd(int argc, char **argv)
|
||||
|
||||
in.buf = g_new(uint8_t, in.bsz);
|
||||
|
||||
for (out_pos = 0; in_pos < size; block_count++) {
|
||||
for (out_pos = 0; in_pos < size; ) {
|
||||
int bytes = (in_pos + in.bsz > size) ? size - in_pos : in.bsz;
|
||||
|
||||
ret = blk_pread(blk1, in_pos, bytes, in.buf, 0);
|
||||
|
||||
@ -139,7 +139,7 @@ SRST
|
||||
interleave requirements before enabling the memory devices.
|
||||
|
||||
``targets.X=target`` provides the mapping to CXL host bridges
|
||||
which may be identified by the id provied in the -device entry.
|
||||
which may be identified by the id provided in the -device entry.
|
||||
Multiple entries are needed to specify all the targets when
|
||||
the fixed memory window represents interleaved memory. X is the
|
||||
target index from 0.
|
||||
@ -362,7 +362,7 @@ SRST
|
||||
\
|
||||
``-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]``
|
||||
\
|
||||
``-numa hmat-lb,initiator=node,target=node,hierarchy=hierarchy,data-type=tpye[,latency=lat][,bandwidth=bw]``
|
||||
``-numa hmat-lb,initiator=node,target=node,hierarchy=hierarchy,data-type=type[,latency=lat][,bandwidth=bw]``
|
||||
\
|
||||
``-numa hmat-cache,node-id=node,size=size,level=level[,associativity=str][,policy=str][,line=size]``
|
||||
Define a NUMA node and assign RAM and VCPUs to it. Set the NUMA
|
||||
@ -1785,7 +1785,7 @@ SRST
|
||||
directory on host is made directly accessible by guest as a pass-through
|
||||
file system by using the 9P network protocol for communication between
|
||||
host and guests, if desired even accessible, shared by several guests
|
||||
simultaniously.
|
||||
simultaneously.
|
||||
|
||||
Note that ``-virtfs`` is actually just a convenience shortcut for its
|
||||
generalized form ``-fsdev -device virtio-9p-pci``.
|
||||
|
||||
@ -49,7 +49,7 @@ stub_ss.add(files('vmstate.c'))
|
||||
stub_ss.add(files('vm-stop.c'))
|
||||
stub_ss.add(files('win32-kbd-hook.c'))
|
||||
stub_ss.add(files('cpu-synchronize-state.c'))
|
||||
if have_block
|
||||
if have_block or have_ga
|
||||
stub_ss.add(files('replay-tools.c'))
|
||||
endif
|
||||
if have_system
|
||||
|
||||
@ -381,7 +381,7 @@ QOSGraphObject *qos_driver_new(QOSGraphNode *node, QOSGraphObject *parent,
|
||||
* mind: only tests with a path down from the actual test case node (leaf) up
|
||||
* to the graph's root node are actually executed by the qtest framework. And
|
||||
* the qtest framework uses QMP to automatically check which QEMU drivers are
|
||||
* actually currently available, and accordingly qos marks certain pathes as
|
||||
* actually currently available, and accordingly qos marks certain paths as
|
||||
* 'unavailable' in such cases (e.g. when QEMU was compiled without support for
|
||||
* a certain feature).
|
||||
*/
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
static QGuestAllocator *alloc;
|
||||
static char *local_test_path;
|
||||
|
||||
/* Concatenates the passed 2 pathes. Returned result must be freed. */
|
||||
/* Concatenates the passed 2 paths. Returned result must be freed. */
|
||||
static char *concat_path(const char* a, const char* b)
|
||||
{
|
||||
return g_build_filename(a, b, NULL);
|
||||
|
||||
@ -68,20 +68,25 @@ if have_system
|
||||
util_ss.add(when: 'CONFIG_LINUX', if_true: files('userfaultfd.c'))
|
||||
endif
|
||||
|
||||
if have_block
|
||||
util_ss.add(files('aiocb.c', 'async.c', 'aio-wait.c'))
|
||||
if have_block or have_ga
|
||||
util_ss.add(files('aiocb.c', 'async.c'))
|
||||
util_ss.add(files('base64.c'))
|
||||
util_ss.add(files('lockcnt.c'))
|
||||
util_ss.add(files('main-loop.c'))
|
||||
util_ss.add(files('qemu-coroutine.c', 'qemu-coroutine-lock.c', 'qemu-coroutine-io.c'))
|
||||
util_ss.add(files('coroutine-@0@.c'.format(config_host['CONFIG_COROUTINE_BACKEND'])))
|
||||
util_ss.add(files('thread-pool.c', 'qemu-timer.c'))
|
||||
util_ss.add(files('qemu-sockets.c'))
|
||||
endif
|
||||
if have_block
|
||||
util_ss.add(files('aio-wait.c'))
|
||||
util_ss.add(files('buffer.c'))
|
||||
util_ss.add(files('bufferiszero.c'))
|
||||
util_ss.add(files('coroutine-@0@.c'.format(config_host['CONFIG_COROUTINE_BACKEND'])))
|
||||
util_ss.add(files('hbitmap.c'))
|
||||
util_ss.add(files('hexdump.c'))
|
||||
util_ss.add(files('iova-tree.c'))
|
||||
util_ss.add(files('iov.c', 'qemu-sockets.c', 'uri.c'))
|
||||
util_ss.add(files('lockcnt.c'))
|
||||
util_ss.add(files('main-loop.c'))
|
||||
util_ss.add(files('iov.c', 'uri.c'))
|
||||
util_ss.add(files('nvdimm-utils.c'))
|
||||
util_ss.add(files('qemu-coroutine.c', 'qemu-coroutine-lock.c', 'qemu-coroutine-io.c'))
|
||||
util_ss.add(when: 'CONFIG_LINUX', if_true: [
|
||||
files('vhost-user-server.c'), vhost_user
|
||||
])
|
||||
@ -89,7 +94,6 @@ if have_block
|
||||
util_ss.add(files('qemu-coroutine-sleep.c'))
|
||||
util_ss.add(files('qemu-co-shared-resource.c'))
|
||||
util_ss.add(files('qemu-co-timeout.c'))
|
||||
util_ss.add(files('thread-pool.c', 'qemu-timer.c'))
|
||||
util_ss.add(files('readline.c'))
|
||||
util_ss.add(files('throttle.c'))
|
||||
util_ss.add(files('timed-average.c'))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user