OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/m68k: implement rtr instruction

Browse Source 
This is needed to boot MacOS ROM.

Pull the condition code and the program counter from the stack.

Operation:

    (SP) -> CCR
    SP + 2 -> SP
    (SP) -> PC
    SP + 4 -> SP

This operation is not privileged.

Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210307212552.523552-1-laurent@vivier.eu>
This commit is contained in:
Laurent Vivier 2021-03-07 22:25:52 +01:00
parent f4abdf3271
commit 6abcec3674
1 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
target/m68k/translate.c
View File

@ -2969,6 +2969,25 @@ DISAS_INSN(rtd)
gen_jmp(s, tmp);
}
DISAS_INSN(rtr)
{
TCGv tmp;
TCGv ccr;
TCGv sp;
sp = tcg_temp_new();
ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
tcg_gen_addi_i32(sp, QREG_SP, 2);
tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
tcg_gen_addi_i32(QREG_SP, sp, 4);
tcg_temp_free(sp);
gen_set_sr(s, ccr, true);
tcg_temp_free(ccr);
gen_jmp(s, tmp);
}
DISAS_INSN(rts)
{
TCGv tmp;
@ -6015,6 +6034,7 @@ void register_m68k_insns (CPUM68KState *env)
BASE(nop, 4e71, ffff);
INSN(rtd, 4e74, ffff, RTD);
BASE(rts, 4e75, ffff);
INSN(rtr, 4e77, ffff, M68000);
BASE(jump, 4e80, ffc0);
BASE(jump, 4ec0, ffc0);
INSN(addsubq, 5000, f080, M68000);