diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target index fcc7b6c1c9..8de005523e 100644 --- a/tests/tcg/tricore/Makefile.softmmu-target +++ b/tests/tcg/tricore/Makefile.softmmu-target @@ -10,6 +10,7 @@ TESTS += test_dvstep.tst TESTS += test_fadd.tst TESTS += test_fmul.tst TESTS += test_ftoi.tst +TESTS += test_madd.tst QEMU_OPTS += -M tricore_testboard -nographic -kernel diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h index e6a41cd1a2..0d76fc403a 100644 --- a/tests/tcg/tricore/macros.h +++ b/tests/tcg/tricore/macros.h @@ -9,6 +9,7 @@ /* Register definitions */ #define DREG_RS1 %d0 #define DREG_RS2 %d1 +#define DREG_RS3 %d4 #define DREG_CALC_RESULT %d1 #define DREG_CALC_PSW %d2 #define DREG_CORRECT_PSW %d3 @@ -85,6 +86,23 @@ test_ ## num: \ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2; \ ) +#define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \ + TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \ + LI(DREG_RS1, rs1); \ + LI(DREG_RS2, rs2); \ + LI(DREG_RS3, rs3); \ + rstv; \ + insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \ + ) + +#define TEST_D_DDI_PSW(insn, num, result, psw, rs1, rs2, imm) \ + TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \ + LI(DREG_RS1, rs1); \ + LI(DREG_RS2, rs2); \ + rstv; \ + insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \ + ) + #define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \ TEST_CASE_E(num, res_lo, res_hi, \ LI(EREG_RS1_LO, rs1_lo); \ diff --git a/tests/tcg/tricore/test_madd.S b/tests/tcg/tricore/test_madd.S new file mode 100644 index 0000000000..5d839772bb --- /dev/null +++ b/tests/tcg/tricore/test_madd.S @@ -0,0 +1,11 @@ +#include "macros.h" +.text +.global _start +_start: + TEST_D_DDI_PSW(madd, 1, 0x0000fffd, 0x60000b80, 0x0000ffff, 0x7fffffff,2) + TEST_D_DDI_PSW(madd, 2, 0xffff7fff, 0x60000b80, 0xffff8001, 0x7fffffff,2) + TEST_D_DDD_PSW(madds.u, 3, 0xffffffff, 0x60000b80, 0x00000000, 0x80000000, \ + 0x80000000) + + TEST_PASSFAIL +