target-arm: Add support for PMU register PMSELR_EL0
This patch adds support for AArch64 register PMSELR_EL0. The existing PMSELR definition is revised accordingly. Signed-off-by: Wei Huang <wei@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Moved #ifndef CONFIG_USER_ONLY to cover new regdefs] Message-id: 1486504171-26807-2-git-send-email-wei@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -309,6 +309,7 @@ typedef struct CPUARMState {
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uint32_t c9_pmovsr; /* perf monitor overflow status */
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uint32_t c9_pmxevtyper; /* perf monitor event type */
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uint32_t c9_pmuserenr; /* perf monitor user enable */
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uint64_t c9_pmselr; /* perf monitor counter selection register */
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uint32_t c9_pminten; /* perf monitor interrupt enables */
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union { /* Memory attribute redirection */
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struct {
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@ -975,6 +975,17 @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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return total_ticks - env->cp15.c15_ccnt;
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}
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static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
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* PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
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* meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
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* accessed.
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*/
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env->cp15.c9_pmselr = value & 0x1f;
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}
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static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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@ -1194,13 +1205,17 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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/* Unimplemented so WI. */
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{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
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.access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
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/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
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* We choose to RAZ/WI.
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*/
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{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
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.accessfn = pmreg_access },
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#ifndef CONFIG_USER_ONLY
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{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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.access = PL0_RW, .type = ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
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.accessfn = pmreg_access, .writefn = pmselr_write,
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.raw_writefn = raw_write},
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{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
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.access = PL0_RW, .accessfn = pmreg_access,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
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.writefn = pmselr_write, .raw_writefn = raw_write, },
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{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write32,
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