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e1000: fix endianness issues

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This patch fixes endianness issues in the e1000 nic emulation, which
currently only works on little endian hosts with little endian targets.

Byte swapping does not depend on host endianness, so this patch remove
the use of cpu_to_le32 and le32_to_cpu functions. It depends on the path
from the CPU to the device, which is currently and *wrongly* implemented
in Qemu as a byteswap on big endian targets. This patch does the same
as in other devices emulation as all the currently implemented targets
work with this implementation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4046 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-03-13 19:18:26 +00:00
parent 5fedc612eb
commit 6b59fc74b5
1 changed files with 16 additions and 7 deletions
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23
hw/e1000.c
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@ -720,8 +720,11 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
E1000State *s = opaque; E1000State *s = opaque;
unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2; unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
if (index < NWRITEOPS && macreg_writeops[index]) if (index < NWRITEOPS && macreg_writeops[index])
macreg_writeops[index](s, index, le32_to_cpu(val)); macreg_writeops[index](s, index, val);
else if (index < NREADOPS && macreg_readops[index]) else if (index < NREADOPS && macreg_readops[index])
DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val); DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
else else
@ -734,7 +737,7 @@ e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{ {
// emulate hw without byte enables: no RMW // emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3, e1000_mmio_writel(opaque, addr & ~3,
cpu_to_le32(le16_to_cpu(val & 0xffff) << (8*(addr & 3)))); (val & 0xffff) << (8*(addr & 3)));
} }
static void static void
@ -742,7 +745,7 @@ e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{ {
// emulate hw without byte enables: no RMW // emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3, e1000_mmio_writel(opaque, addr & ~3,
cpu_to_le32((val & 0xff) << (8*(addr & 3)))); (val & 0xff) << (8*(addr & 3)));
} }
static uint32_t static uint32_t
@ -752,7 +755,13 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2; unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
if (index < NREADOPS && macreg_readops[index]) if (index < NREADOPS && macreg_readops[index])
return cpu_to_le32(macreg_readops[index](s, index)); {
uint32_t val = macreg_readops[index](s, index);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
return val;
}
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
return 0; return 0;
} }
@ -760,15 +769,15 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
static uint32_t static uint32_t
e1000_mmio_readb(void *opaque, target_phys_addr_t addr) e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
{ {
return (le32_to_cpu(e1000_mmio_readl(opaque, addr & ~3)) >> return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xff; (8 * (addr & 3))) & 0xff;
} }
static uint32_t static uint32_t
e1000_mmio_readw(void *opaque, target_phys_addr_t addr) e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
{ {
return cpu_to_le16((le32_to_cpu(e1000_mmio_readl(opaque, addr & ~3)) >> return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xffff); (8 * (addr & 3))) & 0xffff;
} }
int mac_regtosave[] = { int mac_regtosave[] = {