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riscv: Add semihosting support for user mode 

This could made testing more easier and ARM/AArch64 has supported on
their linux user mode too, so I think it should be reasonable.

Verified GCC testsuite with newlib/semihosting.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210107170717.2098982-7-keithp@keithp.com>
Message-Id: <20210108224256.2321-18-alex.bennee@linaro.org>
This commit is contained in:
Kito Cheng 2021-01-08 22:42:53 +00:00 committed by Alex Bennée
parent a10b9d93ec
commit 6b80cb25b4
1 changed files with 5 additions and 0 deletions
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5
linux-user/riscv/cpu_loop.c
View File

@ -23,6 +23,7 @@
#include "qemu.h"
#include "cpu_loop-common.h"
#include "elf.h"
#include "hw/semihosting/common-semi.h"
void cpu_loop(CPURISCVState *env)
{
@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env)
sigcode = TARGET_SEGV_MAPERR;
sigaddr = env->badaddr;
break;
case RISCV_EXCP_SEMIHOST:
env->gpr[xA0] = do_common_semihosting(cs);
env->pc += 4;
break;
case EXCP_DEBUG:
gdbstep:
signum = TARGET_SIGTRAP;