target/riscv: rvv-1.0: whole register move instructions
Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-40-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -650,6 +650,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
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vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
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vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
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vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
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vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
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vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
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vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
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vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
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vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
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vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
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vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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@ -3259,3 +3259,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
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}
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}
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return false;
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return false;
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}
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}
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/*
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* Whole Vector Register Move Instructions ignore vtype and vl setting.
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* Thus, we don't need to check vill bit. (Section 16.6)
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*/
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#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
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static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
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{ \
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if (require_rvv(s) && \
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QEMU_IS_ALIGNED(a->rd, LEN) && \
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QEMU_IS_ALIGNED(a->rs2, LEN)) { \
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/* EEW = 8 */ \
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tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
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vreg_ofs(s, a->rs2), \
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s->vlen / 8 * LEN, s->vlen / 8 * LEN); \
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mark_vs_dirty(s); \
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return true; \
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} \
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return false; \
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}
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GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
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GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
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GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
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GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
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