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Remove ctx->env ptr, add TriCore gdb stub 

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Merge remote-tracking branch 'remotes/bkoppelmann2/tags/pull-tricore-20200601' into staging

Remove ctx->env ptr, add TriCore gdb stub

# gpg: Signature made Mon 01 Jun 2020 16:06:35 BST
# gpg:                using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14
# gpg:                issuer "kbastian@mail.uni-paderborn.de"
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full]
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E  6E37 0AD2 C639 6B69 CA14

* remotes/bkoppelmann2/tags/pull-tricore-20200601:
  target/tricore: Implement gdbstub
  target/tricore: Implement tricore_cpu_get_phys_page_debug
  target/tricore: Raise EXCP_DEBUG in gen_goto_tb() for singlestep
  target/tricore: Move translate feature check to ctx
  target/tricore: Don't save pc in generate_qemu_excp

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-06-01 19:19:18 +01:00
parent 7ea32024c6 d127de3baa
commit 6bb228190e
6 changed files with 208 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/tricore/Makefile.objs
View File

@ -1 +1 @@
obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o
obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o gdbstub.o

20
target/tricore/cpu.c
View File

@ -23,19 +23,16 @@
#include "exec/exec-all.h"
#include "qemu/error-report.h"
static hwaddr tricore_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs)
{
error_report("function cpu_get_phys_page_attrs_debug not "
"implemented, aborting");
return -1;
}
static inline void set_feature(CPUTriCoreState *env, int feature)
{
env->features |= 1ULL << feature;
}
static gchar *tricore_gdb_arch_name(CPUState *cs)
{
return g_strdup("tricore");
}
static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
@ -158,10 +155,15 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = tricore_cpu_class_by_name;
cc->has_work = tricore_cpu_has_work;
cc->gdb_read_register = tricore_cpu_gdb_read_register;
cc->gdb_write_register = tricore_cpu_gdb_write_register;
cc->gdb_num_core_regs = 44;
cc->gdb_arch_name = tricore_gdb_arch_name;
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_attrs_debug = tricore_cpu_get_phys_page_attrs_debug;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->tcg_initialize = tricore_tcg_init;
cc->tlb_fill = tricore_cpu_tlb_fill;
}

2
target/tricore/cpu.h
View File

@ -353,6 +353,8 @@ enum {
uint32_t psw_read(CPUTriCoreState *env);
void psw_write(CPUTriCoreState *env, uint32_t val);
int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
void fpu_set_state(CPUTriCoreState *env);

139
target/tricore/gdbstub.c Normal file
View File

@ -0,0 +1,139 @@
/*
* TriCore gdb server stub
*
* Copyright (c) 2019 Bastian Koppelmann, Paderborn University
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "exec/gdbstub.h"
#define LCX_REGNUM 32
#define FCX_REGNUM 33
#define PCXI_REGNUM 34
#define TRICORE_PSW_REGNUM 35
#define TRICORE_PC_REGNUM 36
#define ICR_REGNUM 37
#define ISP_REGNUM 38
#define BTV_REGNUM 39
#define BIV_REGNUM 40
#define SYSCON_REGNUM 41
#define PMUCON0_REGNUM 42
#define DMUCON_REGNUM 43
static uint32_t tricore_cpu_gdb_read_csfr(CPUTriCoreState *env, int n)
{
switch (n) {
case LCX_REGNUM:
return env->LCX;
case FCX_REGNUM:
return env->FCX;
case PCXI_REGNUM:
return env->PCXI;
case TRICORE_PSW_REGNUM:
return psw_read(env);
case TRICORE_PC_REGNUM:
return env->PC;
case ICR_REGNUM:
return env->ICR;
case ISP_REGNUM:
return env->ISP;
case BTV_REGNUM:
return env->BTV;
case BIV_REGNUM:
return env->BIV;
case SYSCON_REGNUM:
return env->SYSCON;
case PMUCON0_REGNUM:
return 0; /* PMUCON0 */
case DMUCON_REGNUM:
return 0; /* DMUCON0 */
default:
return 0;
}
}
static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n,
uint32_t val)
{
switch (n) {
case LCX_REGNUM:
env->LCX = val;
break;
case FCX_REGNUM:
env->FCX = val;
break;
case PCXI_REGNUM:
env->PCXI = val;
break;
case TRICORE_PSW_REGNUM:
psw_write(env, val);
break;
case TRICORE_PC_REGNUM:
env->PC = val;
break;
case ICR_REGNUM:
env->ICR = val;
break;
case ISP_REGNUM:
env->ISP = val;
break;
case BTV_REGNUM:
env->BTV = val;
break;
case BIV_REGNUM:
env->BIV = val;
break;
case SYSCON_REGNUM:
env->SYSCON = val;
break;
}
}
int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;
if (n < 16) { /* data registers */
return gdb_get_reg32(mem_buf, env->gpr_d[n]);
} else if (n < 32) { /* address registers */
return gdb_get_reg32(mem_buf, env->gpr_a[n - 16]);
} else { /* csfr */
return gdb_get_reg32(mem_buf, tricore_cpu_gdb_read_csfr(env, n));
}
return 0;
}
int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;
uint32_t tmp;
tmp = ldl_p(mem_buf);
if (n < 16) { /* data registers */
env->gpr_d[n] = tmp;
} else if (n < 32) { /* address registers */
env->gpr_d[n - 16] = tmp;
} else {
tricore_cpu_gdb_write_csfr(env, n, tmp);
}
return 4;
}

13
target/tricore/helper.c
View File

@ -42,6 +42,19 @@ static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
return ret;
}
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
hwaddr phys_addr;
int prot;
int mmu_idx = cpu_mmu_index(&cpu->env, false);
if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
return -1;
}
return phys_addr;
}
#endif
/* TODO: Add exeption support*/

79
target/tricore/translate.c
View File

@ -66,14 +66,19 @@ static const char *regnames_d[] = {
typedef struct DisasContext {
DisasContextBase base;
CPUTriCoreState *env;
target_ulong pc_succ_insn;
uint32_t opcode;
/* Routine used to access memory */
int mem_idx;
uint32_t hflags, saved_hflags;
uint64_t features;
} DisasContext;
static int has_feature(DisasContext *ctx, int feature)
{
return (ctx->features & (1ULL << feature)) != 0;
}
enum {
MODE_LL = 0,
MODE_LU = 1,
@ -370,7 +375,7 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
These makros also specify in which ISA version the csfr was introduced. */
#define R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (tricore_feature(ctx->env, FEATURE)) { \
if (has_feature(ctx, FEATURE)) { \
tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
@ -395,7 +400,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
since no execption occurs */
#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
case ADDRESS: \
if (tricore_feature(ctx->env, FEATURE)) { \
if (has_feature(ctx, FEATURE)) { \
tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
} \
break;
@ -3158,7 +3163,7 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
} else {
gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
@ -3173,7 +3178,7 @@ gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
{
TCGv_i64 ret = tcg_temp_new_i64();
if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
} else {
gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
@ -3233,6 +3238,14 @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
#endif
}
static void generate_qemu_excp(DisasContext *ctx, int excp)
{
TCGv_i32 tmp = tcg_const_i32(excp);
gen_helper_qemu_excp(cpu_env, tmp);
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(tmp);
}
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (use_goto_tb(ctx, dest)) {
@ -3242,7 +3255,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
} else {
gen_save_pc(dest);
if (ctx->base.singlestep_enabled) {
/* raise exception debug */
generate_qemu_excp(ctx, EXCP_DEBUG);
}
tcg_gen_exit_tb(NULL, 0);
}
@ -3261,15 +3274,6 @@ static void generate_trap(DisasContext *ctx, int class, int tin)
tcg_temp_free(tintemp);
}
static void generate_qemu_excp(DisasContext *ctx, int excp)
{
TCGv_i32 tmp = tcg_const_i32(excp);
gen_save_pc(ctx->base.pc_next);
gen_helper_qemu_excp(cpu_env, tmp);
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(tmp);
}
static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
TCGv r2, int16_t address)
{
@ -3656,7 +3660,7 @@ static void decode_src_opc(DisasContext *ctx, int op1)
tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
break;
case OPC1_16_SRC_MOV_E:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
} else {
@ -4107,7 +4111,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
break;
case OPC1_16_SBC_JEQ2:
case OPC1_16_SBC_JNE2:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
address = MASK_OP_SBC_DISP4(ctx->opcode);
const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
@ -4125,7 +4129,7 @@ static void decode_16Bit_opc(DisasContext *ctx)
/* SBR-format */
case OPC1_16_SBR_JEQ2:
case OPC1_16_SBR_JNE2:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
r1 = MASK_OP_SBR_S2(ctx->opcode);
address = MASK_OP_SBR_DISP4(ctx->opcode);
gen_compute_branch(ctx, op1, r1, 0, 0, address);
@ -4705,13 +4709,13 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF:
if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC:
if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
if (has_feature(ctx, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@ -4719,7 +4723,7 @@ static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
break;
case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC:
if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
if (has_feature(ctx, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@ -5373,7 +5377,7 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
break;
case OPC1_32_BOL_ST_A_LONGOFF:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@ -5383,42 +5387,42 @@ static void decode_bol_opc(DisasContext *ctx, int32_t op1)
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
break;
case OPC1_32_BOL_LD_B_LONGOFF:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_BU_LONGOFF:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_H_LONGOFF:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_HU_LONGOFF:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_B_LONGOFF:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_H_LONGOFF:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
@ -6023,7 +6027,7 @@ static void decode_rlc_opc(DisasContext *ctx,
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
break;
case OPC1_32_RLC_MOV_64:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r2);
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
@ -6249,7 +6253,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_MOV_64:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
temp = tcg_temp_new();
CHECK_REG_PAIR(r3);
@ -6263,7 +6267,7 @@ static void decode_rr_accumulator(DisasContext *ctx)
}
break;
case OPC2_32_RR_MOVS_64:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
CHECK_REG_PAIR(r3);
tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
@ -6603,7 +6607,7 @@ static void decode_rr_divide(DisasContext *ctx)
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
tcg_gen_abs_tl(temp, temp3);
tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
@ -6636,7 +6640,7 @@ static void decode_rr_divide(DisasContext *ctx)
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) {
if (!has_feature(ctx, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
tcg_gen_abs_tl(temp, temp3);
tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
@ -6699,14 +6703,14 @@ static void decode_rr_divide(DisasContext *ctx)
gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CRC32:
if (tricore_feature(ctx->env, TRICORE_FEATURE_161)) {
if (has_feature(ctx, TRICORE_FEATURE_161)) {
gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_DIV:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
} else {
@ -6714,7 +6718,7 @@ static void decode_rr_divide(DisasContext *ctx)
}
break;
case OPC2_32_RR_DIV_U:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
@ -8412,7 +8416,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
gen_helper_svlcx(cpu_env);
break;
case OPC2_32_SYS_RESTORE:
if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) {
if (has_feature(ctx, TRICORE_FEATURE_16)) {
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
(ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
@ -8793,6 +8797,7 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
CPUTriCoreState *env = cs->env_ptr;
ctx->mem_idx = cpu_mmu_index(env, false);
ctx->hflags = (uint32_t)ctx->base.tb->flags;
ctx->features = env->features;
}
static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)