target/nios2: Update helper_eret for shadow registers
When CRS = 0, we restore from estatus; otherwise from sstatus. Update for the new CRS. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-56-richard.henderson@linaro.org>
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@ -82,6 +82,7 @@ enum {
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R_FP = 28,
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R_EA = 29,
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R_BA = 30,
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R_SSTATUS = 30,
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R_RA = 31,
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};
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@ -73,14 +73,18 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
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}
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/*
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* Both estatus and bstatus have no constraints on write;
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* None of estatus, bstatus, or sstatus have constraints on write;
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* do not allow reserved fields in status to be set.
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* TODO: more than this is required for shadow registers.
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* When shadow registers are enabled, eret *does* restore CRS.
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* Rather than testing eic_present to decide, mask CRS out of
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* the set of readonly fields.
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*/
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new_status &= cpu->cr_state[CR_STATUS].writable;
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new_status &= cpu->cr_state[CR_STATUS].writable |
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(cpu->cr_state[CR_STATUS].readonly & R_CR_STATUS_CRS_MASK);
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env->ctrl[CR_STATUS] = new_status;
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env->pc = new_pc;
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nios2_update_crs(env);
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cpu_loop_exit(cs);
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}
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@ -496,11 +496,14 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
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#ifdef CONFIG_USER_ONLY
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g_assert_not_reached();
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#else
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TCGv tmp = tcg_temp_new();
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
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gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
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tcg_temp_free(tmp);
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if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) {
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TCGv tmp = tcg_temp_new();
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
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gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
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tcg_temp_free(tmp);
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} else {
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gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA));
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}
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dc->base.is_jmp = DISAS_NORETURN;
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#endif
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}
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