accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0
Rename to match tlb_flush_range_locked. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210509151618.2331764-8-f4bug@amsat.org Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -764,9 +764,8 @@ typedef struct {
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uint16_t bits;
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} TLBFlushRangeData;
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static void
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tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu,
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TLBFlushRangeData d)
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static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
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TLBFlushRangeData d)
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{
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CPUArchState *env = cpu->env_ptr;
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int mmu_idx;
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@ -793,7 +792,7 @@ static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
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run_on_cpu_data data)
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{
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TLBFlushRangeData *d = data.host_ptr;
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tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d);
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tlb_flush_range_by_mmuidx_async_0(cpu, *d);
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g_free(d);
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}
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@ -824,7 +823,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
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d.bits = bits;
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if (qemu_cpu_is_self(cpu)) {
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tlb_flush_page_bits_by_mmuidx_async_0(cpu, d);
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tlb_flush_range_by_mmuidx_async_0(cpu, d);
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} else {
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/* Otherwise allocate a structure, freed by the worker. */
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TLBFlushRangeData *p = g_memdup(&d, sizeof(d));
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@ -876,7 +875,7 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
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}
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}
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tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d);
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tlb_flush_range_by_mmuidx_async_0(src_cpu, d);
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}
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void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
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