hw/usb: fix tab indentation
The TABs should be replaced with spaces, to make sure that we have a consistent coding style with an indentation of 4 spaces everywhere. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370 Signed-off-by: Amarjargal Gundjalam <amarjargal16@gmail.com> Message-Id: <6c993f57800f8fef7a910074620f6e80e077a3d1.1666707782.git.amarjargal16@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Amarjargal Gundjalam
Thomas Huth
parent
a076a3dcbf
commit
6c10e08a4f
@ -54,44 +54,44 @@ struct USBHubState {
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#define TYPE_USB_HUB "usb-hub"
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OBJECT_DECLARE_SIMPLE_TYPE(USBHubState, USB_HUB)
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#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
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#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
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#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
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#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
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#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
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#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
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#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
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#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
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#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
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#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
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#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
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#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
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#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
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#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
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#define PORT_STAT_CONNECTION 0x0001
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#define PORT_STAT_ENABLE 0x0002
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#define PORT_STAT_SUSPEND 0x0004
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#define PORT_STAT_OVERCURRENT 0x0008
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#define PORT_STAT_RESET 0x0010
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#define PORT_STAT_POWER 0x0100
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#define PORT_STAT_LOW_SPEED 0x0200
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#define PORT_STAT_CONNECTION 0x0001
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#define PORT_STAT_ENABLE 0x0002
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#define PORT_STAT_SUSPEND 0x0004
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#define PORT_STAT_OVERCURRENT 0x0008
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#define PORT_STAT_RESET 0x0010
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#define PORT_STAT_POWER 0x0100
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#define PORT_STAT_LOW_SPEED 0x0200
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#define PORT_STAT_HIGH_SPEED 0x0400
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#define PORT_STAT_TEST 0x0800
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#define PORT_STAT_INDICATOR 0x1000
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#define PORT_STAT_C_CONNECTION 0x0001
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#define PORT_STAT_C_ENABLE 0x0002
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#define PORT_STAT_C_SUSPEND 0x0004
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#define PORT_STAT_C_OVERCURRENT 0x0008
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#define PORT_STAT_C_RESET 0x0010
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#define PORT_STAT_C_CONNECTION 0x0001
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#define PORT_STAT_C_ENABLE 0x0002
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#define PORT_STAT_C_SUSPEND 0x0004
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#define PORT_STAT_C_OVERCURRENT 0x0008
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#define PORT_STAT_C_RESET 0x0010
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#define PORT_CONNECTION 0
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#define PORT_ENABLE 1
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#define PORT_SUSPEND 2
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#define PORT_OVERCURRENT 3
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#define PORT_RESET 4
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#define PORT_POWER 8
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#define PORT_LOWSPEED 9
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#define PORT_HIGHSPEED 10
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#define PORT_C_CONNECTION 16
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#define PORT_C_ENABLE 17
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#define PORT_C_SUSPEND 18
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#define PORT_C_OVERCURRENT 19
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#define PORT_C_RESET 20
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#define PORT_CONNECTION 0
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#define PORT_ENABLE 1
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#define PORT_SUSPEND 2
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#define PORT_OVERCURRENT 3
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#define PORT_RESET 4
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#define PORT_POWER 8
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#define PORT_LOWSPEED 9
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#define PORT_HIGHSPEED 10
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#define PORT_C_CONNECTION 16
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#define PORT_C_ENABLE 17
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#define PORT_C_SUSPEND 18
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#define PORT_C_OVERCURRENT 19
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#define PORT_C_RESET 20
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#define PORT_TEST 21
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#define PORT_INDICATOR 22
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@ -155,13 +155,13 @@ static const USBDesc desc_hub = {
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static const uint8_t qemu_hub_hub_descriptor[] =
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{
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0x00, /* u8 bLength; patched in later */
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0x29, /* u8 bDescriptorType; Hub-descriptor */
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0x00, /* u8 bNbrPorts; (patched later) */
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0x0a, /* u16 wHubCharacteristics; */
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0x00, /* (per-port OC, no power switching) */
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0x01, /* u8 bPwrOn2pwrGood; 2ms */
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0x00 /* u8 bHubContrCurrent; 0 mA */
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0x00, /* u8 bLength; patched in later */
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0x29, /* u8 bDescriptorType; Hub-descriptor */
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0x00, /* u8 bNbrPorts; (patched later) */
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0x0a, /* u16 wHubCharacteristics; */
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0x00, /* (per-port OC, no power switching) */
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0x01, /* u8 bPwrOn2pwrGood; 2ms */
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0x00 /* u8 bHubContrCurrent; 0 mA */
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/* DeviceRemovable and PortPwrCtrlMask patched in later */
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};
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@ -52,7 +52,7 @@
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#define RNDIS_PRODUCT_NUM 0xa4a2 /* Ethernet/RNDIS Gadget */
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enum usbstring_idx {
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STRING_MANUFACTURER = 1,
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STRING_MANUFACTURER = 1,
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STRING_PRODUCT,
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STRING_ETHADDR,
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STRING_DATA,
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@ -64,39 +64,39 @@ enum usbstring_idx {
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STRING_SERIALNUMBER,
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};
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#define DEV_CONFIG_VALUE 1 /* CDC or a subset */
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#define DEV_RNDIS_CONFIG_VALUE 2 /* RNDIS; optional */
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#define DEV_CONFIG_VALUE 1 /* CDC or a subset */
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#define DEV_RNDIS_CONFIG_VALUE 2 /* RNDIS; optional */
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#define USB_CDC_SUBCLASS_ACM 0x02
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#define USB_CDC_SUBCLASS_ETHERNET 0x06
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#define USB_CDC_SUBCLASS_ACM 0x02
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#define USB_CDC_SUBCLASS_ETHERNET 0x06
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#define USB_CDC_PROTO_NONE 0
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#define USB_CDC_ACM_PROTO_VENDOR 0xff
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#define USB_CDC_PROTO_NONE 0
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#define USB_CDC_ACM_PROTO_VENDOR 0xff
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#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
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#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
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#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
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#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
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#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
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#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
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#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
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#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
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#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
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#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
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#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
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#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
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#define USB_CDC_REQ_SET_LINE_CODING 0x20
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#define USB_CDC_REQ_GET_LINE_CODING 0x21
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#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
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#define USB_CDC_REQ_SEND_BREAK 0x23
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#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
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#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
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#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
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#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
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#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
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#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
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#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
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#define USB_CDC_REQ_SET_LINE_CODING 0x20
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#define USB_CDC_REQ_GET_LINE_CODING 0x21
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#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
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#define USB_CDC_REQ_SEND_BREAK 0x23
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#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
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#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
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#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
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#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
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#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
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#define USB_CDC_NETWORK_CONNECTION 0x00
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#define USB_CDC_NETWORK_CONNECTION 0x00
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#define LOG2_STATUS_INTERVAL_MSEC 5 /* 1 << 5 == 32 msec */
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#define STATUS_BYTECOUNT 16 /* 8 byte header + data */
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#define LOG2_STATUS_INTERVAL_MSEC 5 /* 1 << 5 == 32 msec */
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#define STATUS_BYTECOUNT 16 /* 8 byte header + data */
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#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
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#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
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static const USBDescStrings usb_net_stringtable = {
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[STRING_MANUFACTURER] = "QEMU",
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@ -306,57 +306,57 @@ static const USBDesc desc_net = {
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/*
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* RNDIS Definitions - in theory not specific to USB.
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*/
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#define RNDIS_MAXIMUM_FRAME_SIZE 1518
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#define RNDIS_MAX_TOTAL_SIZE 1558
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#define RNDIS_MAXIMUM_FRAME_SIZE 1518
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#define RNDIS_MAX_TOTAL_SIZE 1558
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/* Remote NDIS Versions */
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#define RNDIS_MAJOR_VERSION 1
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#define RNDIS_MINOR_VERSION 0
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#define RNDIS_MAJOR_VERSION 1
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#define RNDIS_MINOR_VERSION 0
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/* Status Values */
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#define RNDIS_STATUS_SUCCESS 0x00000000U /* Success */
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#define RNDIS_STATUS_FAILURE 0xc0000001U /* Unspecified error */
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#define RNDIS_STATUS_INVALID_DATA 0xc0010015U /* Invalid data */
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#define RNDIS_STATUS_NOT_SUPPORTED 0xc00000bbU /* Unsupported request */
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#define RNDIS_STATUS_MEDIA_CONNECT 0x4001000bU /* Device connected */
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#define RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000cU /* Device disconnected */
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#define RNDIS_STATUS_SUCCESS 0x00000000U /* Success */
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#define RNDIS_STATUS_FAILURE 0xc0000001U /* Unspecified error */
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#define RNDIS_STATUS_INVALID_DATA 0xc0010015U /* Invalid data */
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#define RNDIS_STATUS_NOT_SUPPORTED 0xc00000bbU /* Unsupported request */
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#define RNDIS_STATUS_MEDIA_CONNECT 0x4001000bU /* Device connected */
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#define RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000cU /* Device disconnected */
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/* Message Set for Connectionless (802.3) Devices */
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enum {
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RNDIS_PACKET_MSG = 1,
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RNDIS_INITIALIZE_MSG = 2, /* Initialize device */
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RNDIS_HALT_MSG = 3,
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RNDIS_QUERY_MSG = 4,
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RNDIS_SET_MSG = 5,
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RNDIS_RESET_MSG = 6,
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RNDIS_INDICATE_STATUS_MSG = 7,
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RNDIS_KEEPALIVE_MSG = 8,
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RNDIS_PACKET_MSG = 1,
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RNDIS_INITIALIZE_MSG = 2, /* Initialize device */
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RNDIS_HALT_MSG = 3,
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RNDIS_QUERY_MSG = 4,
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RNDIS_SET_MSG = 5,
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RNDIS_RESET_MSG = 6,
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RNDIS_INDICATE_STATUS_MSG = 7,
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RNDIS_KEEPALIVE_MSG = 8,
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};
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/* Message completion */
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enum {
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RNDIS_INITIALIZE_CMPLT = 0x80000002U,
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RNDIS_QUERY_CMPLT = 0x80000004U,
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RNDIS_SET_CMPLT = 0x80000005U,
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RNDIS_RESET_CMPLT = 0x80000006U,
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RNDIS_KEEPALIVE_CMPLT = 0x80000008U,
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RNDIS_INITIALIZE_CMPLT = 0x80000002U,
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RNDIS_QUERY_CMPLT = 0x80000004U,
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RNDIS_SET_CMPLT = 0x80000005U,
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RNDIS_RESET_CMPLT = 0x80000006U,
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RNDIS_KEEPALIVE_CMPLT = 0x80000008U,
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};
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/* Device Flags */
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enum {
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RNDIS_DF_CONNECTIONLESS = 1,
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RNDIS_DF_CONNECTIONORIENTED = 2,
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RNDIS_DF_CONNECTIONLESS = 1,
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RNDIS_DF_CONNECTIONORIENTED = 2,
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};
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#define RNDIS_MEDIUM_802_3 0x00000000U
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#define RNDIS_MEDIUM_802_3 0x00000000U
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/* from drivers/net/sk98lin/h/skgepnmi.h */
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#define OID_PNP_CAPABILITIES 0xfd010100
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#define OID_PNP_SET_POWER 0xfd010101
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#define OID_PNP_QUERY_POWER 0xfd010102
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#define OID_PNP_ADD_WAKE_UP_PATTERN 0xfd010103
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#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xfd010104
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#define OID_PNP_ENABLE_WAKE_UP 0xfd010106
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#define OID_PNP_CAPABILITIES 0xfd010100
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#define OID_PNP_SET_POWER 0xfd010101
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#define OID_PNP_QUERY_POWER 0xfd010102
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#define OID_PNP_ADD_WAKE_UP_PATTERN 0xfd010103
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#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xfd010104
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#define OID_PNP_ENABLE_WAKE_UP 0xfd010106
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typedef uint32_t le32;
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@ -494,88 +494,88 @@ enum rndis_state
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/* from ndis.h */
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enum ndis_oid {
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/* Required Object IDs (OIDs) */
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OID_GEN_SUPPORTED_LIST = 0x00010101,
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OID_GEN_HARDWARE_STATUS = 0x00010102,
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OID_GEN_MEDIA_SUPPORTED = 0x00010103,
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OID_GEN_MEDIA_IN_USE = 0x00010104,
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OID_GEN_MAXIMUM_LOOKAHEAD = 0x00010105,
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OID_GEN_MAXIMUM_FRAME_SIZE = 0x00010106,
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OID_GEN_LINK_SPEED = 0x00010107,
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OID_GEN_TRANSMIT_BUFFER_SPACE = 0x00010108,
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OID_GEN_RECEIVE_BUFFER_SPACE = 0x00010109,
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OID_GEN_TRANSMIT_BLOCK_SIZE = 0x0001010a,
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OID_GEN_RECEIVE_BLOCK_SIZE = 0x0001010b,
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OID_GEN_VENDOR_ID = 0x0001010c,
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OID_GEN_VENDOR_DESCRIPTION = 0x0001010d,
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OID_GEN_CURRENT_PACKET_FILTER = 0x0001010e,
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OID_GEN_CURRENT_LOOKAHEAD = 0x0001010f,
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OID_GEN_DRIVER_VERSION = 0x00010110,
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OID_GEN_MAXIMUM_TOTAL_SIZE = 0x00010111,
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OID_GEN_PROTOCOL_OPTIONS = 0x00010112,
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OID_GEN_MAC_OPTIONS = 0x00010113,
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OID_GEN_MEDIA_CONNECT_STATUS = 0x00010114,
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OID_GEN_MAXIMUM_SEND_PACKETS = 0x00010115,
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OID_GEN_VENDOR_DRIVER_VERSION = 0x00010116,
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OID_GEN_SUPPORTED_GUIDS = 0x00010117,
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OID_GEN_NETWORK_LAYER_ADDRESSES = 0x00010118,
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OID_GEN_TRANSPORT_HEADER_OFFSET = 0x00010119,
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OID_GEN_MACHINE_NAME = 0x0001021a,
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OID_GEN_RNDIS_CONFIG_PARAMETER = 0x0001021b,
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OID_GEN_VLAN_ID = 0x0001021c,
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OID_GEN_SUPPORTED_LIST = 0x00010101,
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OID_GEN_HARDWARE_STATUS = 0x00010102,
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OID_GEN_MEDIA_SUPPORTED = 0x00010103,
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OID_GEN_MEDIA_IN_USE = 0x00010104,
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OID_GEN_MAXIMUM_LOOKAHEAD = 0x00010105,
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OID_GEN_MAXIMUM_FRAME_SIZE = 0x00010106,
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OID_GEN_LINK_SPEED = 0x00010107,
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OID_GEN_TRANSMIT_BUFFER_SPACE = 0x00010108,
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OID_GEN_RECEIVE_BUFFER_SPACE = 0x00010109,
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OID_GEN_TRANSMIT_BLOCK_SIZE = 0x0001010a,
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OID_GEN_RECEIVE_BLOCK_SIZE = 0x0001010b,
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OID_GEN_VENDOR_ID = 0x0001010c,
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OID_GEN_VENDOR_DESCRIPTION = 0x0001010d,
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OID_GEN_CURRENT_PACKET_FILTER = 0x0001010e,
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OID_GEN_CURRENT_LOOKAHEAD = 0x0001010f,
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OID_GEN_DRIVER_VERSION = 0x00010110,
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OID_GEN_MAXIMUM_TOTAL_SIZE = 0x00010111,
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OID_GEN_PROTOCOL_OPTIONS = 0x00010112,
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OID_GEN_MAC_OPTIONS = 0x00010113,
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OID_GEN_MEDIA_CONNECT_STATUS = 0x00010114,
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OID_GEN_MAXIMUM_SEND_PACKETS = 0x00010115,
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OID_GEN_VENDOR_DRIVER_VERSION = 0x00010116,
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OID_GEN_SUPPORTED_GUIDS = 0x00010117,
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OID_GEN_NETWORK_LAYER_ADDRESSES = 0x00010118,
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OID_GEN_TRANSPORT_HEADER_OFFSET = 0x00010119,
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OID_GEN_MACHINE_NAME = 0x0001021a,
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OID_GEN_RNDIS_CONFIG_PARAMETER = 0x0001021b,
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OID_GEN_VLAN_ID = 0x0001021c,
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/* Optional OIDs */
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OID_GEN_MEDIA_CAPABILITIES = 0x00010201,
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OID_GEN_PHYSICAL_MEDIUM = 0x00010202,
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OID_GEN_MEDIA_CAPABILITIES = 0x00010201,
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OID_GEN_PHYSICAL_MEDIUM = 0x00010202,
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/* Required statistics OIDs */
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OID_GEN_XMIT_OK = 0x00020101,
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OID_GEN_RCV_OK = 0x00020102,
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OID_GEN_XMIT_ERROR = 0x00020103,
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OID_GEN_RCV_ERROR = 0x00020104,
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OID_GEN_RCV_NO_BUFFER = 0x00020105,
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OID_GEN_XMIT_OK = 0x00020101,
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OID_GEN_RCV_OK = 0x00020102,
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OID_GEN_XMIT_ERROR = 0x00020103,
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OID_GEN_RCV_ERROR = 0x00020104,
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OID_GEN_RCV_NO_BUFFER = 0x00020105,
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/* Optional statistics OIDs */
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OID_GEN_DIRECTED_BYTES_XMIT = 0x00020201,
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OID_GEN_DIRECTED_FRAMES_XMIT = 0x00020202,
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OID_GEN_MULTICAST_BYTES_XMIT = 0x00020203,
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OID_GEN_MULTICAST_FRAMES_XMIT = 0x00020204,
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OID_GEN_BROADCAST_BYTES_XMIT = 0x00020205,
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OID_GEN_BROADCAST_FRAMES_XMIT = 0x00020206,
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OID_GEN_DIRECTED_BYTES_RCV = 0x00020207,
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OID_GEN_DIRECTED_FRAMES_RCV = 0x00020208,
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OID_GEN_MULTICAST_BYTES_RCV = 0x00020209,
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OID_GEN_MULTICAST_FRAMES_RCV = 0x0002020a,
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OID_GEN_BROADCAST_BYTES_RCV = 0x0002020b,
|
||||
OID_GEN_BROADCAST_FRAMES_RCV = 0x0002020c,
|
||||
OID_GEN_RCV_CRC_ERROR = 0x0002020d,
|
||||
OID_GEN_TRANSMIT_QUEUE_LENGTH = 0x0002020e,
|
||||
OID_GEN_GET_TIME_CAPS = 0x0002020f,
|
||||
OID_GEN_GET_NETCARD_TIME = 0x00020210,
|
||||
OID_GEN_NETCARD_LOAD = 0x00020211,
|
||||
OID_GEN_DEVICE_PROFILE = 0x00020212,
|
||||
OID_GEN_INIT_TIME_MS = 0x00020213,
|
||||
OID_GEN_RESET_COUNTS = 0x00020214,
|
||||
OID_GEN_MEDIA_SENSE_COUNTS = 0x00020215,
|
||||
OID_GEN_FRIENDLY_NAME = 0x00020216,
|
||||
OID_GEN_MINIPORT_INFO = 0x00020217,
|
||||
OID_GEN_RESET_VERIFY_PARAMETERS = 0x00020218,
|
||||
OID_GEN_DIRECTED_BYTES_XMIT = 0x00020201,
|
||||
OID_GEN_DIRECTED_FRAMES_XMIT = 0x00020202,
|
||||
OID_GEN_MULTICAST_BYTES_XMIT = 0x00020203,
|
||||
OID_GEN_MULTICAST_FRAMES_XMIT = 0x00020204,
|
||||
OID_GEN_BROADCAST_BYTES_XMIT = 0x00020205,
|
||||
OID_GEN_BROADCAST_FRAMES_XMIT = 0x00020206,
|
||||
OID_GEN_DIRECTED_BYTES_RCV = 0x00020207,
|
||||
OID_GEN_DIRECTED_FRAMES_RCV = 0x00020208,
|
||||
OID_GEN_MULTICAST_BYTES_RCV = 0x00020209,
|
||||
OID_GEN_MULTICAST_FRAMES_RCV = 0x0002020a,
|
||||
OID_GEN_BROADCAST_BYTES_RCV = 0x0002020b,
|
||||
OID_GEN_BROADCAST_FRAMES_RCV = 0x0002020c,
|
||||
OID_GEN_RCV_CRC_ERROR = 0x0002020d,
|
||||
OID_GEN_TRANSMIT_QUEUE_LENGTH = 0x0002020e,
|
||||
OID_GEN_GET_TIME_CAPS = 0x0002020f,
|
||||
OID_GEN_GET_NETCARD_TIME = 0x00020210,
|
||||
OID_GEN_NETCARD_LOAD = 0x00020211,
|
||||
OID_GEN_DEVICE_PROFILE = 0x00020212,
|
||||
OID_GEN_INIT_TIME_MS = 0x00020213,
|
||||
OID_GEN_RESET_COUNTS = 0x00020214,
|
||||
OID_GEN_MEDIA_SENSE_COUNTS = 0x00020215,
|
||||
OID_GEN_FRIENDLY_NAME = 0x00020216,
|
||||
OID_GEN_MINIPORT_INFO = 0x00020217,
|
||||
OID_GEN_RESET_VERIFY_PARAMETERS = 0x00020218,
|
||||
|
||||
/* IEEE 802.3 (Ethernet) OIDs */
|
||||
OID_802_3_PERMANENT_ADDRESS = 0x01010101,
|
||||
OID_802_3_CURRENT_ADDRESS = 0x01010102,
|
||||
OID_802_3_MULTICAST_LIST = 0x01010103,
|
||||
OID_802_3_MAXIMUM_LIST_SIZE = 0x01010104,
|
||||
OID_802_3_MAC_OPTIONS = 0x01010105,
|
||||
OID_802_3_RCV_ERROR_ALIGNMENT = 0x01020101,
|
||||
OID_802_3_XMIT_ONE_COLLISION = 0x01020102,
|
||||
OID_802_3_XMIT_MORE_COLLISIONS = 0x01020103,
|
||||
OID_802_3_XMIT_DEFERRED = 0x01020201,
|
||||
OID_802_3_XMIT_MAX_COLLISIONS = 0x01020202,
|
||||
OID_802_3_RCV_OVERRUN = 0x01020203,
|
||||
OID_802_3_XMIT_UNDERRUN = 0x01020204,
|
||||
OID_802_3_XMIT_HEARTBEAT_FAILURE = 0x01020205,
|
||||
OID_802_3_XMIT_TIMES_CRS_LOST = 0x01020206,
|
||||
OID_802_3_XMIT_LATE_COLLISIONS = 0x01020207,
|
||||
OID_802_3_PERMANENT_ADDRESS = 0x01010101,
|
||||
OID_802_3_CURRENT_ADDRESS = 0x01010102,
|
||||
OID_802_3_MULTICAST_LIST = 0x01010103,
|
||||
OID_802_3_MAXIMUM_LIST_SIZE = 0x01010104,
|
||||
OID_802_3_MAC_OPTIONS = 0x01010105,
|
||||
OID_802_3_RCV_ERROR_ALIGNMENT = 0x01020101,
|
||||
OID_802_3_XMIT_ONE_COLLISION = 0x01020102,
|
||||
OID_802_3_XMIT_MORE_COLLISIONS = 0x01020103,
|
||||
OID_802_3_XMIT_DEFERRED = 0x01020201,
|
||||
OID_802_3_XMIT_MAX_COLLISIONS = 0x01020202,
|
||||
OID_802_3_RCV_OVERRUN = 0x01020203,
|
||||
OID_802_3_XMIT_UNDERRUN = 0x01020204,
|
||||
OID_802_3_XMIT_HEARTBEAT_FAILURE = 0x01020205,
|
||||
OID_802_3_XMIT_TIMES_CRS_LOST = 0x01020206,
|
||||
OID_802_3_XMIT_LATE_COLLISIONS = 0x01020207,
|
||||
};
|
||||
|
||||
static const uint32_t oid_supported_list[] =
|
||||
@ -618,13 +618,13 @@ static const uint32_t oid_supported_list[] =
|
||||
OID_802_3_XMIT_MORE_COLLISIONS,
|
||||
};
|
||||
|
||||
#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA (1 << 0)
|
||||
#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED (1 << 1)
|
||||
#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND (1 << 2)
|
||||
#define NDIS_MAC_OPTION_NO_LOOPBACK (1 << 3)
|
||||
#define NDIS_MAC_OPTION_FULL_DUPLEX (1 << 4)
|
||||
#define NDIS_MAC_OPTION_EOTX_INDICATION (1 << 5)
|
||||
#define NDIS_MAC_OPTION_8021P_PRIORITY (1 << 6)
|
||||
#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA (1 << 0)
|
||||
#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED (1 << 1)
|
||||
#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND (1 << 2)
|
||||
#define NDIS_MAC_OPTION_NO_LOOPBACK (1 << 3)
|
||||
#define NDIS_MAC_OPTION_FULL_DUPLEX (1 << 4)
|
||||
#define NDIS_MAC_OPTION_EOTX_INDICATION (1 << 5)
|
||||
#define NDIS_MAC_OPTION_8021P_PRIORITY (1 << 6)
|
||||
|
||||
struct rndis_response {
|
||||
QTAILQ_ENTRY(rndis_response) entries;
|
||||
@ -1375,12 +1375,12 @@ static void usb_net_realize(USBDevice *dev, Error **errp)
|
||||
s->rndis_state = RNDIS_UNINITIALIZED;
|
||||
QTAILQ_INIT(&s->rndis_resp);
|
||||
|
||||
s->medium = 0; /* NDIS_MEDIUM_802_3 */
|
||||
s->medium = 0; /* NDIS_MEDIUM_802_3 */
|
||||
s->speed = 1000000; /* 100MBps, in 100Bps units */
|
||||
s->media_state = 0; /* NDIS_MEDIA_STATE_CONNECTED */;
|
||||
s->media_state = 0; /* NDIS_MEDIA_STATE_CONNECTED */;
|
||||
s->filter = 0;
|
||||
s->vendorid = 0x1234;
|
||||
s->connection = 1; /* Connected */
|
||||
s->connection = 1; /* Connected */
|
||||
s->intr = usb_ep_get(dev, USB_TOKEN_IN, 1);
|
||||
s->bulk_in = usb_ep_get(dev, USB_TOKEN_IN, 2);
|
||||
|
||||
|
||||
@ -36,8 +36,8 @@
|
||||
#include "qom/object.h"
|
||||
|
||||
/* Interface requests */
|
||||
#define WACOM_GET_REPORT 0x2101
|
||||
#define WACOM_SET_REPORT 0x2109
|
||||
#define WACOM_GET_REPORT 0x2101
|
||||
#define WACOM_SET_REPORT 0x2109
|
||||
|
||||
struct USBWacomState {
|
||||
USBDevice dev;
|
||||
|
||||
@ -28,227 +28,227 @@
|
||||
#include "hw/hw.h"
|
||||
|
||||
/* Common USB registers */
|
||||
#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
|
||||
#define MUSB_HDRC_POWER 0x01 /* 8-bit */
|
||||
#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
|
||||
#define MUSB_HDRC_POWER 0x01 /* 8-bit */
|
||||
|
||||
#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
|
||||
#define MUSB_HDRC_INTRRX 0x04
|
||||
#define MUSB_HDRC_INTRTXE 0x06
|
||||
#define MUSB_HDRC_INTRRXE 0x08
|
||||
#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
|
||||
#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
|
||||
#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
|
||||
#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
|
||||
#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
|
||||
#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
|
||||
#define MUSB_HDRC_INTRRX 0x04
|
||||
#define MUSB_HDRC_INTRTXE 0x06
|
||||
#define MUSB_HDRC_INTRRXE 0x08
|
||||
#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
|
||||
#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
|
||||
#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
|
||||
#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
|
||||
#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
|
||||
|
||||
/* Per-EP registers in indexed mode */
|
||||
#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
|
||||
#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
|
||||
|
||||
/* EP FIFOs */
|
||||
#define MUSB_HDRC_FIFO 0x20
|
||||
#define MUSB_HDRC_FIFO 0x20
|
||||
|
||||
/* Additional Control Registers */
|
||||
#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
|
||||
#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
|
||||
|
||||
/* These are indexed */
|
||||
#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
|
||||
#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
|
||||
#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
|
||||
#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
|
||||
#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
|
||||
#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
|
||||
#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
|
||||
#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
|
||||
|
||||
/* Some more registers */
|
||||
#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
|
||||
#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
|
||||
#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
|
||||
#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
|
||||
|
||||
/* Added in HDRC 1.9(?) & MHDRC 1.4 */
|
||||
/* ULPI pass-through */
|
||||
#define MUSB_HDRC_ULPI_VBUSCTL 0x70
|
||||
#define MUSB_HDRC_ULPI_REGDATA 0x74
|
||||
#define MUSB_HDRC_ULPI_REGADDR 0x75
|
||||
#define MUSB_HDRC_ULPI_REGCTL 0x76
|
||||
#define MUSB_HDRC_ULPI_VBUSCTL 0x70
|
||||
#define MUSB_HDRC_ULPI_REGDATA 0x74
|
||||
#define MUSB_HDRC_ULPI_REGADDR 0x75
|
||||
#define MUSB_HDRC_ULPI_REGCTL 0x76
|
||||
|
||||
/* Extended config & PHY control */
|
||||
#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
|
||||
#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
|
||||
#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
|
||||
#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
|
||||
#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
|
||||
#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
|
||||
#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
|
||||
#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
|
||||
#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
|
||||
#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
|
||||
#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
|
||||
#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
|
||||
#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
|
||||
#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
|
||||
|
||||
/* Per-EP BUSCTL registers */
|
||||
#define MUSB_HDRC_BUSCTL 0x80
|
||||
#define MUSB_HDRC_BUSCTL 0x80
|
||||
|
||||
/* Per-EP registers in flat mode */
|
||||
#define MUSB_HDRC_EP 0x100
|
||||
#define MUSB_HDRC_EP 0x100
|
||||
|
||||
/* offsets to registers in flat model */
|
||||
#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
|
||||
#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
|
||||
#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
|
||||
#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
|
||||
#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
|
||||
#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
|
||||
#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
|
||||
#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
|
||||
#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
|
||||
#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
|
||||
#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
|
||||
#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
|
||||
#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
|
||||
#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
|
||||
#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
|
||||
#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
|
||||
#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
|
||||
#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
|
||||
#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
|
||||
#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
|
||||
#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
|
||||
|
||||
/* "Bus control" registers */
|
||||
#define MUSB_HDRC_TXFUNCADDR 0x00
|
||||
#define MUSB_HDRC_TXHUBADDR 0x02
|
||||
#define MUSB_HDRC_TXHUBPORT 0x03
|
||||
#define MUSB_HDRC_TXFUNCADDR 0x00
|
||||
#define MUSB_HDRC_TXHUBADDR 0x02
|
||||
#define MUSB_HDRC_TXHUBPORT 0x03
|
||||
|
||||
#define MUSB_HDRC_RXFUNCADDR 0x04
|
||||
#define MUSB_HDRC_RXHUBADDR 0x06
|
||||
#define MUSB_HDRC_RXHUBPORT 0x07
|
||||
#define MUSB_HDRC_RXFUNCADDR 0x04
|
||||
#define MUSB_HDRC_RXHUBADDR 0x06
|
||||
#define MUSB_HDRC_RXHUBPORT 0x07
|
||||
|
||||
/*
|
||||
* MUSBHDRC Register bit masks
|
||||
*/
|
||||
|
||||
/* POWER */
|
||||
#define MGC_M_POWER_ISOUPDATE 0x80
|
||||
#define MGC_M_POWER_SOFTCONN 0x40
|
||||
#define MGC_M_POWER_HSENAB 0x20
|
||||
#define MGC_M_POWER_HSMODE 0x10
|
||||
#define MGC_M_POWER_RESET 0x08
|
||||
#define MGC_M_POWER_RESUME 0x04
|
||||
#define MGC_M_POWER_SUSPENDM 0x02
|
||||
#define MGC_M_POWER_ENSUSPEND 0x01
|
||||
#define MGC_M_POWER_ISOUPDATE 0x80
|
||||
#define MGC_M_POWER_SOFTCONN 0x40
|
||||
#define MGC_M_POWER_HSENAB 0x20
|
||||
#define MGC_M_POWER_HSMODE 0x10
|
||||
#define MGC_M_POWER_RESET 0x08
|
||||
#define MGC_M_POWER_RESUME 0x04
|
||||
#define MGC_M_POWER_SUSPENDM 0x02
|
||||
#define MGC_M_POWER_ENSUSPEND 0x01
|
||||
|
||||
/* INTRUSB */
|
||||
#define MGC_M_INTR_SUSPEND 0x01
|
||||
#define MGC_M_INTR_RESUME 0x02
|
||||
#define MGC_M_INTR_RESET 0x04
|
||||
#define MGC_M_INTR_BABBLE 0x04
|
||||
#define MGC_M_INTR_SOF 0x08
|
||||
#define MGC_M_INTR_CONNECT 0x10
|
||||
#define MGC_M_INTR_DISCONNECT 0x20
|
||||
#define MGC_M_INTR_SESSREQ 0x40
|
||||
#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
|
||||
#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
|
||||
#define MGC_M_INTR_SUSPEND 0x01
|
||||
#define MGC_M_INTR_RESUME 0x02
|
||||
#define MGC_M_INTR_RESET 0x04
|
||||
#define MGC_M_INTR_BABBLE 0x04
|
||||
#define MGC_M_INTR_SOF 0x08
|
||||
#define MGC_M_INTR_CONNECT 0x10
|
||||
#define MGC_M_INTR_DISCONNECT 0x20
|
||||
#define MGC_M_INTR_SESSREQ 0x40
|
||||
#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
|
||||
#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
|
||||
|
||||
/* DEVCTL */
|
||||
#define MGC_M_DEVCTL_BDEVICE 0x80
|
||||
#define MGC_M_DEVCTL_FSDEV 0x40
|
||||
#define MGC_M_DEVCTL_LSDEV 0x20
|
||||
#define MGC_M_DEVCTL_VBUS 0x18
|
||||
#define MGC_S_DEVCTL_VBUS 3
|
||||
#define MGC_M_DEVCTL_HM 0x04
|
||||
#define MGC_M_DEVCTL_HR 0x02
|
||||
#define MGC_M_DEVCTL_SESSION 0x01
|
||||
#define MGC_M_DEVCTL_BDEVICE 0x80
|
||||
#define MGC_M_DEVCTL_FSDEV 0x40
|
||||
#define MGC_M_DEVCTL_LSDEV 0x20
|
||||
#define MGC_M_DEVCTL_VBUS 0x18
|
||||
#define MGC_S_DEVCTL_VBUS 3
|
||||
#define MGC_M_DEVCTL_HM 0x04
|
||||
#define MGC_M_DEVCTL_HR 0x02
|
||||
#define MGC_M_DEVCTL_SESSION 0x01
|
||||
|
||||
/* TESTMODE */
|
||||
#define MGC_M_TEST_FORCE_HOST 0x80
|
||||
#define MGC_M_TEST_FIFO_ACCESS 0x40
|
||||
#define MGC_M_TEST_FORCE_FS 0x20
|
||||
#define MGC_M_TEST_FORCE_HS 0x10
|
||||
#define MGC_M_TEST_PACKET 0x08
|
||||
#define MGC_M_TEST_K 0x04
|
||||
#define MGC_M_TEST_J 0x02
|
||||
#define MGC_M_TEST_SE0_NAK 0x01
|
||||
#define MGC_M_TEST_FORCE_HOST 0x80
|
||||
#define MGC_M_TEST_FIFO_ACCESS 0x40
|
||||
#define MGC_M_TEST_FORCE_FS 0x20
|
||||
#define MGC_M_TEST_FORCE_HS 0x10
|
||||
#define MGC_M_TEST_PACKET 0x08
|
||||
#define MGC_M_TEST_K 0x04
|
||||
#define MGC_M_TEST_J 0x02
|
||||
#define MGC_M_TEST_SE0_NAK 0x01
|
||||
|
||||
/* CSR0 */
|
||||
#define MGC_M_CSR0_FLUSHFIFO 0x0100
|
||||
#define MGC_M_CSR0_TXPKTRDY 0x0002
|
||||
#define MGC_M_CSR0_RXPKTRDY 0x0001
|
||||
#define MGC_M_CSR0_FLUSHFIFO 0x0100
|
||||
#define MGC_M_CSR0_TXPKTRDY 0x0002
|
||||
#define MGC_M_CSR0_RXPKTRDY 0x0001
|
||||
|
||||
/* CSR0 in Peripheral mode */
|
||||
#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
|
||||
#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
|
||||
#define MGC_M_CSR0_P_SENDSTALL 0x0020
|
||||
#define MGC_M_CSR0_P_SETUPEND 0x0010
|
||||
#define MGC_M_CSR0_P_DATAEND 0x0008
|
||||
#define MGC_M_CSR0_P_SENTSTALL 0x0004
|
||||
#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
|
||||
#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
|
||||
#define MGC_M_CSR0_P_SENDSTALL 0x0020
|
||||
#define MGC_M_CSR0_P_SETUPEND 0x0010
|
||||
#define MGC_M_CSR0_P_DATAEND 0x0008
|
||||
#define MGC_M_CSR0_P_SENTSTALL 0x0004
|
||||
|
||||
/* CSR0 in Host mode */
|
||||
#define MGC_M_CSR0_H_NO_PING 0x0800
|
||||
#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
|
||||
#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
|
||||
#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
|
||||
#define MGC_M_CSR0_H_STATUSPKT 0x0040
|
||||
#define MGC_M_CSR0_H_REQPKT 0x0020
|
||||
#define MGC_M_CSR0_H_ERROR 0x0010
|
||||
#define MGC_M_CSR0_H_SETUPPKT 0x0008
|
||||
#define MGC_M_CSR0_H_RXSTALL 0x0004
|
||||
#define MGC_M_CSR0_H_NO_PING 0x0800
|
||||
#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
|
||||
#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
|
||||
#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
|
||||
#define MGC_M_CSR0_H_STATUSPKT 0x0040
|
||||
#define MGC_M_CSR0_H_REQPKT 0x0020
|
||||
#define MGC_M_CSR0_H_ERROR 0x0010
|
||||
#define MGC_M_CSR0_H_SETUPPKT 0x0008
|
||||
#define MGC_M_CSR0_H_RXSTALL 0x0004
|
||||
|
||||
/* CONFIGDATA */
|
||||
#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
|
||||
#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
|
||||
#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
|
||||
#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
|
||||
#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
|
||||
#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
|
||||
#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
|
||||
#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
|
||||
#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
|
||||
#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
|
||||
#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
|
||||
#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
|
||||
#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
|
||||
#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
|
||||
#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
|
||||
#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
|
||||
|
||||
/* TXCSR in Peripheral and Host mode */
|
||||
#define MGC_M_TXCSR_AUTOSET 0x8000
|
||||
#define MGC_M_TXCSR_ISO 0x4000
|
||||
#define MGC_M_TXCSR_MODE 0x2000
|
||||
#define MGC_M_TXCSR_DMAENAB 0x1000
|
||||
#define MGC_M_TXCSR_FRCDATATOG 0x0800
|
||||
#define MGC_M_TXCSR_DMAMODE 0x0400
|
||||
#define MGC_M_TXCSR_CLRDATATOG 0x0040
|
||||
#define MGC_M_TXCSR_FLUSHFIFO 0x0008
|
||||
#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
|
||||
#define MGC_M_TXCSR_TXPKTRDY 0x0001
|
||||
#define MGC_M_TXCSR_AUTOSET 0x8000
|
||||
#define MGC_M_TXCSR_ISO 0x4000
|
||||
#define MGC_M_TXCSR_MODE 0x2000
|
||||
#define MGC_M_TXCSR_DMAENAB 0x1000
|
||||
#define MGC_M_TXCSR_FRCDATATOG 0x0800
|
||||
#define MGC_M_TXCSR_DMAMODE 0x0400
|
||||
#define MGC_M_TXCSR_CLRDATATOG 0x0040
|
||||
#define MGC_M_TXCSR_FLUSHFIFO 0x0008
|
||||
#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
|
||||
#define MGC_M_TXCSR_TXPKTRDY 0x0001
|
||||
|
||||
/* TXCSR in Peripheral mode */
|
||||
#define MGC_M_TXCSR_P_INCOMPTX 0x0080
|
||||
#define MGC_M_TXCSR_P_SENTSTALL 0x0020
|
||||
#define MGC_M_TXCSR_P_SENDSTALL 0x0010
|
||||
#define MGC_M_TXCSR_P_UNDERRUN 0x0004
|
||||
#define MGC_M_TXCSR_P_INCOMPTX 0x0080
|
||||
#define MGC_M_TXCSR_P_SENTSTALL 0x0020
|
||||
#define MGC_M_TXCSR_P_SENDSTALL 0x0010
|
||||
#define MGC_M_TXCSR_P_UNDERRUN 0x0004
|
||||
|
||||
/* TXCSR in Host mode */
|
||||
#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
|
||||
#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
|
||||
#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
|
||||
#define MGC_M_TXCSR_H_RXSTALL 0x0020
|
||||
#define MGC_M_TXCSR_H_ERROR 0x0004
|
||||
#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
|
||||
#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
|
||||
#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
|
||||
#define MGC_M_TXCSR_H_RXSTALL 0x0020
|
||||
#define MGC_M_TXCSR_H_ERROR 0x0004
|
||||
|
||||
/* RXCSR in Peripheral and Host mode */
|
||||
#define MGC_M_RXCSR_AUTOCLEAR 0x8000
|
||||
#define MGC_M_RXCSR_DMAENAB 0x2000
|
||||
#define MGC_M_RXCSR_DISNYET 0x1000
|
||||
#define MGC_M_RXCSR_DMAMODE 0x0800
|
||||
#define MGC_M_RXCSR_INCOMPRX 0x0100
|
||||
#define MGC_M_RXCSR_CLRDATATOG 0x0080
|
||||
#define MGC_M_RXCSR_FLUSHFIFO 0x0010
|
||||
#define MGC_M_RXCSR_DATAERROR 0x0008
|
||||
#define MGC_M_RXCSR_FIFOFULL 0x0002
|
||||
#define MGC_M_RXCSR_RXPKTRDY 0x0001
|
||||
#define MGC_M_RXCSR_AUTOCLEAR 0x8000
|
||||
#define MGC_M_RXCSR_DMAENAB 0x2000
|
||||
#define MGC_M_RXCSR_DISNYET 0x1000
|
||||
#define MGC_M_RXCSR_DMAMODE 0x0800
|
||||
#define MGC_M_RXCSR_INCOMPRX 0x0100
|
||||
#define MGC_M_RXCSR_CLRDATATOG 0x0080
|
||||
#define MGC_M_RXCSR_FLUSHFIFO 0x0010
|
||||
#define MGC_M_RXCSR_DATAERROR 0x0008
|
||||
#define MGC_M_RXCSR_FIFOFULL 0x0002
|
||||
#define MGC_M_RXCSR_RXPKTRDY 0x0001
|
||||
|
||||
/* RXCSR in Peripheral mode */
|
||||
#define MGC_M_RXCSR_P_ISO 0x4000
|
||||
#define MGC_M_RXCSR_P_SENTSTALL 0x0040
|
||||
#define MGC_M_RXCSR_P_SENDSTALL 0x0020
|
||||
#define MGC_M_RXCSR_P_OVERRUN 0x0004
|
||||
#define MGC_M_RXCSR_P_ISO 0x4000
|
||||
#define MGC_M_RXCSR_P_SENTSTALL 0x0040
|
||||
#define MGC_M_RXCSR_P_SENDSTALL 0x0020
|
||||
#define MGC_M_RXCSR_P_OVERRUN 0x0004
|
||||
|
||||
/* RXCSR in Host mode */
|
||||
#define MGC_M_RXCSR_H_AUTOREQ 0x4000
|
||||
#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
|
||||
#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
|
||||
#define MGC_M_RXCSR_H_RXSTALL 0x0040
|
||||
#define MGC_M_RXCSR_H_REQPKT 0x0020
|
||||
#define MGC_M_RXCSR_H_ERROR 0x0004
|
||||
#define MGC_M_RXCSR_H_AUTOREQ 0x4000
|
||||
#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
|
||||
#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
|
||||
#define MGC_M_RXCSR_H_RXSTALL 0x0040
|
||||
#define MGC_M_RXCSR_H_REQPKT 0x0020
|
||||
#define MGC_M_RXCSR_H_ERROR 0x0004
|
||||
|
||||
/* HUBADDR */
|
||||
#define MGC_M_HUBADDR_MULTI_TT 0x80
|
||||
#define MGC_M_HUBADDR_MULTI_TT 0x80
|
||||
|
||||
/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
|
||||
#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
|
||||
#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
|
||||
#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
|
||||
#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
|
||||
#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
|
||||
#define MGC_M_ULPI_REGCTL_REG 0x01
|
||||
#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
|
||||
#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
|
||||
#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
|
||||
#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
|
||||
#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
|
||||
#define MGC_M_ULPI_REGCTL_REG 0x01
|
||||
|
||||
/* #define MUSB_DEBUG */
|
||||
|
||||
@ -296,7 +296,7 @@ struct MUSBEndPoint {
|
||||
uint8_t interval[2];
|
||||
uint8_t config;
|
||||
uint8_t fifosize;
|
||||
int timeout[2]; /* Always in microframes */
|
||||
int timeout[2]; /* Always in microframes */
|
||||
|
||||
uint8_t *buf[2];
|
||||
int fifolen[2];
|
||||
@ -542,7 +542,7 @@ static void musb_cb_tick1(void *opaque)
|
||||
ep->delayed_cb[1](&ep->packey[1].p, opaque);
|
||||
}
|
||||
|
||||
#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
|
||||
#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
|
||||
|
||||
static void musb_schedule_cb(USBPort *port, USBPacket *packey)
|
||||
{
|
||||
@ -1323,7 +1323,7 @@ static void musb_writeb(void *opaque, hwaddr addr, uint32_t value)
|
||||
/* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
|
||||
if ((value & MGC_M_POWER_HSENAB) &&
|
||||
s->port.dev->speed == USB_SPEED_HIGH)
|
||||
s->power |= MGC_M_POWER_HSMODE; /* Success */
|
||||
s->power |= MGC_M_POWER_HSMODE; /* Success */
|
||||
/* Restart frame counting. */
|
||||
}
|
||||
if (value & MGC_M_POWER_SUSPENDM) {
|
||||
|
||||
@ -1,150 +1,150 @@
|
||||
/*
|
||||
* Prolific PL2303 USB to serial adaptor driver header file
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#define BENQ_VENDOR_ID 0x04a5
|
||||
#define BENQ_PRODUCT_ID_S81 0x4027
|
||||
#define BENQ_VENDOR_ID 0x04a5
|
||||
#define BENQ_PRODUCT_ID_S81 0x4027
|
||||
|
||||
#define PL2303_VENDOR_ID 0x067b
|
||||
#define PL2303_PRODUCT_ID 0x2303
|
||||
#define PL2303_PRODUCT_ID_RSAQ2 0x04bb
|
||||
#define PL2303_PRODUCT_ID_DCU11 0x1234
|
||||
#define PL2303_PRODUCT_ID_PHAROS 0xaaa0
|
||||
#define PL2303_PRODUCT_ID_RSAQ3 0xaaa2
|
||||
#define PL2303_PRODUCT_ID_ALDIGA 0x0611
|
||||
#define PL2303_PRODUCT_ID_MMX 0x0612
|
||||
#define PL2303_PRODUCT_ID_GPRS 0x0609
|
||||
#define PL2303_PRODUCT_ID_HCR331 0x331a
|
||||
#define PL2303_PRODUCT_ID_MOTOROLA 0x0307
|
||||
#define PL2303_VENDOR_ID 0x067b
|
||||
#define PL2303_PRODUCT_ID 0x2303
|
||||
#define PL2303_PRODUCT_ID_RSAQ2 0x04bb
|
||||
#define PL2303_PRODUCT_ID_DCU11 0x1234
|
||||
#define PL2303_PRODUCT_ID_PHAROS 0xaaa0
|
||||
#define PL2303_PRODUCT_ID_RSAQ3 0xaaa2
|
||||
#define PL2303_PRODUCT_ID_ALDIGA 0x0611
|
||||
#define PL2303_PRODUCT_ID_MMX 0x0612
|
||||
#define PL2303_PRODUCT_ID_GPRS 0x0609
|
||||
#define PL2303_PRODUCT_ID_HCR331 0x331a
|
||||
#define PL2303_PRODUCT_ID_MOTOROLA 0x0307
|
||||
|
||||
#define ATEN_VENDOR_ID 0x0557
|
||||
#define ATEN_VENDOR_ID2 0x0547
|
||||
#define ATEN_PRODUCT_ID 0x2008
|
||||
#define ATEN_VENDOR_ID 0x0557
|
||||
#define ATEN_VENDOR_ID2 0x0547
|
||||
#define ATEN_PRODUCT_ID 0x2008
|
||||
|
||||
#define IODATA_VENDOR_ID 0x04bb
|
||||
#define IODATA_PRODUCT_ID 0x0a03
|
||||
#define IODATA_PRODUCT_ID_RSAQ5 0x0a0e
|
||||
#define IODATA_VENDOR_ID 0x04bb
|
||||
#define IODATA_PRODUCT_ID 0x0a03
|
||||
#define IODATA_PRODUCT_ID_RSAQ5 0x0a0e
|
||||
|
||||
#define ELCOM_VENDOR_ID 0x056e
|
||||
#define ELCOM_PRODUCT_ID 0x5003
|
||||
#define ELCOM_PRODUCT_ID_UCSGT 0x5004
|
||||
#define ELCOM_VENDOR_ID 0x056e
|
||||
#define ELCOM_PRODUCT_ID 0x5003
|
||||
#define ELCOM_PRODUCT_ID_UCSGT 0x5004
|
||||
|
||||
#define ITEGNO_VENDOR_ID 0x0eba
|
||||
#define ITEGNO_PRODUCT_ID 0x1080
|
||||
#define ITEGNO_PRODUCT_ID_2080 0x2080
|
||||
#define ITEGNO_VENDOR_ID 0x0eba
|
||||
#define ITEGNO_PRODUCT_ID 0x1080
|
||||
#define ITEGNO_PRODUCT_ID_2080 0x2080
|
||||
|
||||
#define MA620_VENDOR_ID 0x0df7
|
||||
#define MA620_PRODUCT_ID 0x0620
|
||||
#define MA620_VENDOR_ID 0x0df7
|
||||
#define MA620_PRODUCT_ID 0x0620
|
||||
|
||||
#define RATOC_VENDOR_ID 0x0584
|
||||
#define RATOC_PRODUCT_ID 0xb000
|
||||
#define RATOC_VENDOR_ID 0x0584
|
||||
#define RATOC_PRODUCT_ID 0xb000
|
||||
|
||||
#define TRIPP_VENDOR_ID 0x2478
|
||||
#define TRIPP_PRODUCT_ID 0x2008
|
||||
#define TRIPP_VENDOR_ID 0x2478
|
||||
#define TRIPP_PRODUCT_ID 0x2008
|
||||
|
||||
#define RADIOSHACK_VENDOR_ID 0x1453
|
||||
#define RADIOSHACK_PRODUCT_ID 0x4026
|
||||
#define RADIOSHACK_VENDOR_ID 0x1453
|
||||
#define RADIOSHACK_PRODUCT_ID 0x4026
|
||||
|
||||
#define DCU10_VENDOR_ID 0x0731
|
||||
#define DCU10_PRODUCT_ID 0x0528
|
||||
#define DCU10_VENDOR_ID 0x0731
|
||||
#define DCU10_PRODUCT_ID 0x0528
|
||||
|
||||
#define SITECOM_VENDOR_ID 0x6189
|
||||
#define SITECOM_PRODUCT_ID 0x2068
|
||||
#define SITECOM_VENDOR_ID 0x6189
|
||||
#define SITECOM_PRODUCT_ID 0x2068
|
||||
|
||||
/* Alcatel OT535/735 USB cable */
|
||||
#define ALCATEL_VENDOR_ID 0x11f7
|
||||
#define ALCATEL_PRODUCT_ID 0x02df
|
||||
#define ALCATEL_VENDOR_ID 0x11f7
|
||||
#define ALCATEL_PRODUCT_ID 0x02df
|
||||
|
||||
/* Samsung I330 phone cradle */
|
||||
#define SAMSUNG_VENDOR_ID 0x04e8
|
||||
#define SAMSUNG_PRODUCT_ID 0x8001
|
||||
#define SAMSUNG_VENDOR_ID 0x04e8
|
||||
#define SAMSUNG_PRODUCT_ID 0x8001
|
||||
|
||||
#define SIEMENS_VENDOR_ID 0x11f5
|
||||
#define SIEMENS_PRODUCT_ID_SX1 0x0001
|
||||
#define SIEMENS_PRODUCT_ID_X65 0x0003
|
||||
#define SIEMENS_PRODUCT_ID_X75 0x0004
|
||||
#define SIEMENS_PRODUCT_ID_EF81 0x0005
|
||||
#define SIEMENS_VENDOR_ID 0x11f5
|
||||
#define SIEMENS_PRODUCT_ID_SX1 0x0001
|
||||
#define SIEMENS_PRODUCT_ID_X65 0x0003
|
||||
#define SIEMENS_PRODUCT_ID_X75 0x0004
|
||||
#define SIEMENS_PRODUCT_ID_EF81 0x0005
|
||||
|
||||
#define SYNTECH_VENDOR_ID 0x0745
|
||||
#define SYNTECH_PRODUCT_ID 0x0001
|
||||
#define SYNTECH_VENDOR_ID 0x0745
|
||||
#define SYNTECH_PRODUCT_ID 0x0001
|
||||
|
||||
/* Nokia CA-42 Cable */
|
||||
#define NOKIA_CA42_VENDOR_ID 0x078b
|
||||
#define NOKIA_CA42_PRODUCT_ID 0x1234
|
||||
#define NOKIA_CA42_VENDOR_ID 0x078b
|
||||
#define NOKIA_CA42_PRODUCT_ID 0x1234
|
||||
|
||||
/* CA-42 CLONE Cable www.ca-42.com chipset: Prolific Technology Inc */
|
||||
#define CA_42_CA42_VENDOR_ID 0x10b5
|
||||
#define CA_42_CA42_PRODUCT_ID 0xac70
|
||||
#define CA_42_CA42_VENDOR_ID 0x10b5
|
||||
#define CA_42_CA42_PRODUCT_ID 0xac70
|
||||
|
||||
#define SAGEM_VENDOR_ID 0x079b
|
||||
#define SAGEM_PRODUCT_ID 0x0027
|
||||
#define SAGEM_VENDOR_ID 0x079b
|
||||
#define SAGEM_PRODUCT_ID 0x0027
|
||||
|
||||
/* Leadtek GPS 9531 (ID 0413:2101) */
|
||||
#define LEADTEK_VENDOR_ID 0x0413
|
||||
#define LEADTEK_9531_PRODUCT_ID 0x2101
|
||||
#define LEADTEK_VENDOR_ID 0x0413
|
||||
#define LEADTEK_9531_PRODUCT_ID 0x2101
|
||||
|
||||
/* USB GSM cable from Speed Dragon Multimedia, Ltd */
|
||||
#define SPEEDDRAGON_VENDOR_ID 0x0e55
|
||||
#define SPEEDDRAGON_PRODUCT_ID 0x110b
|
||||
#define SPEEDDRAGON_VENDOR_ID 0x0e55
|
||||
#define SPEEDDRAGON_PRODUCT_ID 0x110b
|
||||
|
||||
/* DATAPILOT Universal-2 Phone Cable */
|
||||
#define DATAPILOT_U2_VENDOR_ID 0x0731
|
||||
#define DATAPILOT_U2_PRODUCT_ID 0x2003
|
||||
#define DATAPILOT_U2_VENDOR_ID 0x0731
|
||||
#define DATAPILOT_U2_PRODUCT_ID 0x2003
|
||||
|
||||
/* Belkin "F5U257" Serial Adapter */
|
||||
#define BELKIN_VENDOR_ID 0x050d
|
||||
#define BELKIN_PRODUCT_ID 0x0257
|
||||
#define BELKIN_VENDOR_ID 0x050d
|
||||
#define BELKIN_PRODUCT_ID 0x0257
|
||||
|
||||
/* Alcor Micro Corp. USB 2.0 TO RS-232 */
|
||||
#define ALCOR_VENDOR_ID 0x058F
|
||||
#define ALCOR_PRODUCT_ID 0x9720
|
||||
#define ALCOR_VENDOR_ID 0x058F
|
||||
#define ALCOR_PRODUCT_ID 0x9720
|
||||
|
||||
/* Willcom WS002IN Data Driver (by NetIndex Inc.) */
|
||||
#define WS002IN_VENDOR_ID 0x11f6
|
||||
#define WS002IN_PRODUCT_ID 0x2001
|
||||
#define WS002IN_VENDOR_ID 0x11f6
|
||||
#define WS002IN_PRODUCT_ID 0x2001
|
||||
|
||||
/* Corega CG-USBRS232R Serial Adapter */
|
||||
#define COREGA_VENDOR_ID 0x07aa
|
||||
#define COREGA_PRODUCT_ID 0x002a
|
||||
#define COREGA_VENDOR_ID 0x07aa
|
||||
#define COREGA_PRODUCT_ID 0x002a
|
||||
|
||||
/* Y.C. Cable U.S.A., Inc - USB to RS-232 */
|
||||
#define YCCABLE_VENDOR_ID 0x05ad
|
||||
#define YCCABLE_PRODUCT_ID 0x0fba
|
||||
#define YCCABLE_VENDOR_ID 0x05ad
|
||||
#define YCCABLE_PRODUCT_ID 0x0fba
|
||||
|
||||
/* "Superial" USB - Serial */
|
||||
#define SUPERIAL_VENDOR_ID 0x5372
|
||||
#define SUPERIAL_PRODUCT_ID 0x2303
|
||||
#define SUPERIAL_VENDOR_ID 0x5372
|
||||
#define SUPERIAL_PRODUCT_ID 0x2303
|
||||
|
||||
/* Hewlett-Packard LD220-HP POS Pole Display */
|
||||
#define HP_VENDOR_ID 0x03f0
|
||||
#define HP_LD220_PRODUCT_ID 0x3524
|
||||
#define HP_VENDOR_ID 0x03f0
|
||||
#define HP_LD220_PRODUCT_ID 0x3524
|
||||
|
||||
/* Cressi Edy (diving computer) PC interface */
|
||||
#define CRESSI_VENDOR_ID 0x04b8
|
||||
#define CRESSI_EDY_PRODUCT_ID 0x0521
|
||||
#define CRESSI_VENDOR_ID 0x04b8
|
||||
#define CRESSI_EDY_PRODUCT_ID 0x0521
|
||||
|
||||
/* Zeagle dive computer interface */
|
||||
#define ZEAGLE_VENDOR_ID 0x04b8
|
||||
#define ZEAGLE_N2ITION3_PRODUCT_ID 0x0522
|
||||
#define ZEAGLE_VENDOR_ID 0x04b8
|
||||
#define ZEAGLE_N2ITION3_PRODUCT_ID 0x0522
|
||||
|
||||
/* Sony, USB data cable for CMD-Jxx mobile phones */
|
||||
#define SONY_VENDOR_ID 0x054c
|
||||
#define SONY_QN3USB_PRODUCT_ID 0x0437
|
||||
#define SONY_VENDOR_ID 0x054c
|
||||
#define SONY_QN3USB_PRODUCT_ID 0x0437
|
||||
|
||||
/* Sanwa KB-USB2 multimeter cable (ID: 11ad:0001) */
|
||||
#define SANWA_VENDOR_ID 0x11ad
|
||||
#define SANWA_PRODUCT_ID 0x0001
|
||||
#define SANWA_VENDOR_ID 0x11ad
|
||||
#define SANWA_PRODUCT_ID 0x0001
|
||||
|
||||
/* ADLINK ND-6530 RS232,RS485 and RS422 adapter */
|
||||
#define ADLINK_VENDOR_ID 0x0b63
|
||||
#define ADLINK_ND6530_PRODUCT_ID 0x6530
|
||||
#define ADLINK_VENDOR_ID 0x0b63
|
||||
#define ADLINK_ND6530_PRODUCT_ID 0x6530
|
||||
|
||||
/* SMART USB Serial Adapter */
|
||||
#define SMART_VENDOR_ID 0x0b8c
|
||||
#define SMART_PRODUCT_ID 0x2303
|
||||
#define SMART_VENDOR_ID 0x0b8c
|
||||
#define SMART_PRODUCT_ID 0x2303
|
||||
|
||||
100
include/hw/usb.h
100
include/hw/usb.h
@ -66,42 +66,42 @@
|
||||
//#define USB_STATE_POWERED 2
|
||||
#define USB_STATE_DEFAULT 3
|
||||
//#define USB_STATE_ADDRESS 4
|
||||
//#define USB_STATE_CONFIGURED 5
|
||||
//#define USB_STATE_CONFIGURED 5
|
||||
#define USB_STATE_SUSPENDED 6
|
||||
|
||||
#define USB_CLASS_AUDIO 1
|
||||
#define USB_CLASS_COMM 2
|
||||
#define USB_CLASS_HID 3
|
||||
#define USB_CLASS_PHYSICAL 5
|
||||
#define USB_CLASS_STILL_IMAGE 6
|
||||
#define USB_CLASS_PRINTER 7
|
||||
#define USB_CLASS_MASS_STORAGE 8
|
||||
#define USB_CLASS_HUB 9
|
||||
#define USB_CLASS_CDC_DATA 0x0a
|
||||
#define USB_CLASS_CSCID 0x0b
|
||||
#define USB_CLASS_CONTENT_SEC 0x0d
|
||||
#define USB_CLASS_APP_SPEC 0xfe
|
||||
#define USB_CLASS_VENDOR_SPEC 0xff
|
||||
#define USB_CLASS_AUDIO 1
|
||||
#define USB_CLASS_COMM 2
|
||||
#define USB_CLASS_HID 3
|
||||
#define USB_CLASS_PHYSICAL 5
|
||||
#define USB_CLASS_STILL_IMAGE 6
|
||||
#define USB_CLASS_PRINTER 7
|
||||
#define USB_CLASS_MASS_STORAGE 8
|
||||
#define USB_CLASS_HUB 9
|
||||
#define USB_CLASS_CDC_DATA 0x0a
|
||||
#define USB_CLASS_CSCID 0x0b
|
||||
#define USB_CLASS_CONTENT_SEC 0x0d
|
||||
#define USB_CLASS_APP_SPEC 0xfe
|
||||
#define USB_CLASS_VENDOR_SPEC 0xff
|
||||
|
||||
#define USB_SUBCLASS_UNDEFINED 0
|
||||
#define USB_SUBCLASS_AUDIO_CONTROL 1
|
||||
#define USB_SUBCLASS_AUDIO_STREAMING 2
|
||||
#define USB_SUBCLASS_AUDIO_MIDISTREAMING 3
|
||||
|
||||
#define USB_DIR_OUT 0
|
||||
#define USB_DIR_IN 0x80
|
||||
#define USB_DIR_OUT 0
|
||||
#define USB_DIR_IN 0x80
|
||||
|
||||
#define USB_TYPE_MASK (0x03 << 5)
|
||||
#define USB_TYPE_STANDARD (0x00 << 5)
|
||||
#define USB_TYPE_CLASS (0x01 << 5)
|
||||
#define USB_TYPE_VENDOR (0x02 << 5)
|
||||
#define USB_TYPE_RESERVED (0x03 << 5)
|
||||
#define USB_TYPE_MASK (0x03 << 5)
|
||||
#define USB_TYPE_STANDARD (0x00 << 5)
|
||||
#define USB_TYPE_CLASS (0x01 << 5)
|
||||
#define USB_TYPE_VENDOR (0x02 << 5)
|
||||
#define USB_TYPE_RESERVED (0x03 << 5)
|
||||
|
||||
#define USB_RECIP_MASK 0x1f
|
||||
#define USB_RECIP_DEVICE 0x00
|
||||
#define USB_RECIP_INTERFACE 0x01
|
||||
#define USB_RECIP_ENDPOINT 0x02
|
||||
#define USB_RECIP_OTHER 0x03
|
||||
#define USB_RECIP_MASK 0x1f
|
||||
#define USB_RECIP_DEVICE 0x00
|
||||
#define USB_RECIP_INTERFACE 0x01
|
||||
#define USB_RECIP_ENDPOINT 0x02
|
||||
#define USB_RECIP_OTHER 0x03
|
||||
|
||||
#define DeviceRequest ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
|
||||
#define DeviceOutRequest ((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
|
||||
@ -126,28 +126,28 @@
|
||||
#define EndpointOutRequest \
|
||||
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_ENDPOINT)<<8)
|
||||
|
||||
#define USB_REQ_GET_STATUS 0x00
|
||||
#define USB_REQ_CLEAR_FEATURE 0x01
|
||||
#define USB_REQ_SET_FEATURE 0x03
|
||||
#define USB_REQ_SET_ADDRESS 0x05
|
||||
#define USB_REQ_GET_DESCRIPTOR 0x06
|
||||
#define USB_REQ_SET_DESCRIPTOR 0x07
|
||||
#define USB_REQ_GET_CONFIGURATION 0x08
|
||||
#define USB_REQ_SET_CONFIGURATION 0x09
|
||||
#define USB_REQ_GET_INTERFACE 0x0A
|
||||
#define USB_REQ_SET_INTERFACE 0x0B
|
||||
#define USB_REQ_SYNCH_FRAME 0x0C
|
||||
#define USB_REQ_GET_STATUS 0x00
|
||||
#define USB_REQ_CLEAR_FEATURE 0x01
|
||||
#define USB_REQ_SET_FEATURE 0x03
|
||||
#define USB_REQ_SET_ADDRESS 0x05
|
||||
#define USB_REQ_GET_DESCRIPTOR 0x06
|
||||
#define USB_REQ_SET_DESCRIPTOR 0x07
|
||||
#define USB_REQ_GET_CONFIGURATION 0x08
|
||||
#define USB_REQ_SET_CONFIGURATION 0x09
|
||||
#define USB_REQ_GET_INTERFACE 0x0A
|
||||
#define USB_REQ_SET_INTERFACE 0x0B
|
||||
#define USB_REQ_SYNCH_FRAME 0x0C
|
||||
#define USB_REQ_SET_SEL 0x30
|
||||
#define USB_REQ_SET_ISOCH_DELAY 0x31
|
||||
|
||||
#define USB_DEVICE_SELF_POWERED 0
|
||||
#define USB_DEVICE_REMOTE_WAKEUP 1
|
||||
#define USB_DEVICE_SELF_POWERED 0
|
||||
#define USB_DEVICE_REMOTE_WAKEUP 1
|
||||
|
||||
#define USB_DT_DEVICE 0x01
|
||||
#define USB_DT_CONFIG 0x02
|
||||
#define USB_DT_STRING 0x03
|
||||
#define USB_DT_INTERFACE 0x04
|
||||
#define USB_DT_ENDPOINT 0x05
|
||||
#define USB_DT_DEVICE 0x01
|
||||
#define USB_DT_CONFIG 0x02
|
||||
#define USB_DT_STRING 0x03
|
||||
#define USB_DT_INTERFACE 0x04
|
||||
#define USB_DT_ENDPOINT 0x05
|
||||
#define USB_DT_DEVICE_QUALIFIER 0x06
|
||||
#define USB_DT_OTHER_SPEED_CONFIG 0x07
|
||||
#define USB_DT_DEBUG 0x0A
|
||||
@ -167,10 +167,10 @@
|
||||
#define USB_CFG_ATT_WAKEUP (1 << 5)
|
||||
#define USB_CFG_ATT_BATTERY (1 << 4)
|
||||
|
||||
#define USB_ENDPOINT_XFER_CONTROL 0
|
||||
#define USB_ENDPOINT_XFER_ISOC 1
|
||||
#define USB_ENDPOINT_XFER_BULK 2
|
||||
#define USB_ENDPOINT_XFER_INT 3
|
||||
#define USB_ENDPOINT_XFER_CONTROL 0
|
||||
#define USB_ENDPOINT_XFER_ISOC 1
|
||||
#define USB_ENDPOINT_XFER_BULK 2
|
||||
#define USB_ENDPOINT_XFER_INT 3
|
||||
#define USB_ENDPOINT_XFER_INVALID 255
|
||||
|
||||
#define USB_INTERFACE_INVALID 255
|
||||
@ -569,9 +569,9 @@ static inline bool usb_device_is_scsi_storage(USBDevice *dev)
|
||||
/* quirks.c */
|
||||
|
||||
/* In bulk endpoints are streaming data sources (iow behave like isoc eps) */
|
||||
#define USB_QUIRK_BUFFER_BULK_IN 0x01
|
||||
#define USB_QUIRK_BUFFER_BULK_IN 0x01
|
||||
/* Bulk pkts in FTDI format, need special handling when combining packets */
|
||||
#define USB_QUIRK_IS_FTDI 0x02
|
||||
#define USB_QUIRK_IS_FTDI 0x02
|
||||
|
||||
int usb_get_quirks(uint16_t vendor_id, uint16_t product_id,
|
||||
uint8_t interface_class, uint8_t interface_subclass,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user