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hexagon: spelling fixes

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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Brian Cain <bcain@quicinc.com>
This commit is contained in:
Michael Tokarev 2023-07-14 14:21:23 +03:00
parent 64a917d5d6
commit 6c67d98c4a
10 changed files with 19 additions and 19 deletions
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2
target/hexagon/README
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@ -239,7 +239,7 @@ helper_funcs_generated.c.inc. There are also several helpers used for debugging
VLIW packet semantics differ from serial semantics in that all input operands
are read, then the operations are performed, then all the results are written.
For exmaple, this packet performs a swap of registers r0 and r1
For example, this packet performs a swap of registers r0 and r1
{ r0 = r1; r1 = r0 }
Note that the result is different if the instructions are executed serially.

2
target/hexagon/fma_emu.c
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@ -415,7 +415,7 @@ static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \
* We want to normalize left until we have a leading one in bit 24 \
* Theoretically, we only need to shift a maximum of one to the left if we \
* shifted out lots of bits from B, or if we had no shift / 1 shift sticky \
* shoudl be 0 \
* should be 0 \
*/ \
while ((int128_getlo(a.mant) & (1ULL << MANTBITS)) == 0) { \
a = accum_norm_left(a); \

2
target/hexagon/idef-parser/README.rst
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@ -440,7 +440,7 @@ interested part of the grammar.
Run-time errors can be divided between lexing and parsing errors, lexing errors
are hard to detect, since the ``var`` token will catch everything which is not
catched by other tokens, but easy to fix, because most of the time a simple
caught by other tokens, but easy to fix, because most of the time a simple
regex editing will be enough.
idef-parser features a fancy parsing error reporting scheme, which for each

2
target/hexagon/idef-parser/idef-parser.h
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@ -73,7 +73,7 @@ typedef struct HexTmp {
} HexTmp;
/**
* Enum of the possible immediated, an immediate is a value which is known
* Enum of the possible immediate, an immediate is a value which is known
* at tinycode generation time, e.g. an integer value, not a TCGv
*/
enum ImmUnionTag {

6
target/hexagon/idef-parser/parser-helpers.c
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@ -459,7 +459,7 @@ static bool try_find_variable(Context *c, YYLTYPE *locp,
return false;
}
/* Calls `try_find_variable` and asserts succcess. */
/* Calls `try_find_variable` and asserts success. */
static void find_variable(Context *c, YYLTYPE *locp,
HexValue *dst,
HexValue *varid)
@ -549,7 +549,7 @@ HexValue gen_bin_cmp(Context *c,
");\n");
break;
default:
fprintf(stderr, "Error in evalutating immediateness!");
fprintf(stderr, "Error in evaluating immediateness!");
abort();
}
return res;
@ -1164,7 +1164,7 @@ void gen_rdeposit_op(Context *c,
{
/*
* Otherwise if the width is not known, we fallback on reimplementing
* desposit in TCG.
* deposit in TCG.
*/
HexValue begin_m = *begin;
HexValue value_m = *value;

8
target/hexagon/imported/alu.idef
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@ -292,16 +292,16 @@ Q6INSN(A4_combineii,"Rdd32=combine(#s8,#U6)",ATTRIBS(),"Set two small immediates
Q6INSN(A2_combine_hh,"Rd32=combine(Rt.H32,Rs.H32)",ATTRIBS(),
"Combine two halfs into a register", {RdV = (fGETUHALF(1,RtV)<<16) | fGETUHALF(1,RsV);})
"Combine two halves into a register", {RdV = (fGETUHALF(1,RtV)<<16) | fGETUHALF(1,RsV);})
Q6INSN(A2_combine_hl,"Rd32=combine(Rt.H32,Rs.L32)",ATTRIBS(),
"Combine two halfs into a register", {RdV = (fGETUHALF(1,RtV)<<16) | fGETUHALF(0,RsV);})
"Combine two halves into a register", {RdV = (fGETUHALF(1,RtV)<<16) | fGETUHALF(0,RsV);})
Q6INSN(A2_combine_lh,"Rd32=combine(Rt.L32,Rs.H32)",ATTRIBS(),
"Combine two halfs into a register", {RdV = (fGETUHALF(0,RtV)<<16) | fGETUHALF(1,RsV);})
"Combine two halves into a register", {RdV = (fGETUHALF(0,RtV)<<16) | fGETUHALF(1,RsV);})
Q6INSN(A2_combine_ll,"Rd32=combine(Rt.L32,Rs.L32)",ATTRIBS(),
"Combine two halfs into a register", {RdV = (fGETUHALF(0,RtV)<<16) | fGETUHALF(0,RsV);})
"Combine two halves into a register", {RdV = (fGETUHALF(0,RtV)<<16) | fGETUHALF(0,RsV);})
Q6INSN(A2_tfril,"Rx.L32=#u16",ATTRIBS(),
"Set low 16-bits, leave upper 16 unchanged",{ fSETHALF(0,RxV,uiV);})

2
target/hexagon/imported/macros.def
View File

@ -902,7 +902,7 @@ DEF_MACRO(
)
DEF_MACRO(
fEA_GPI, /* Calculate EA with Global Poitner + Immediate */
fEA_GPI, /* Calculate EA with Global Pointer + Immediate */
do { EA=fREAD_GP()+IMM; fGP_DOCHKPAGECROSS(fREAD_GP(),EA); } while (0),
()
)

10
target/hexagon/imported/mmvec/ext.idef
View File

@ -17,7 +17,7 @@
/******************************************************************************
*
* HOYA: MULTI MEDIA INSTRUCITONS
* HOYA: MULTI MEDIA INSTRUCTIONS
*
******************************************************************************/
@ -295,7 +295,7 @@ MMVEC_COND_EACH_EA(vS32Ub,"Unaligned Vector Store",ATTRIBS(ATTR_VMEMU,A_STORE,A_
MMVEC_EACH_EA(vS32b_new,"Aligned Vector Store New",ATTRIBS(ATTR_VMEM,A_STORE,A_CVI_NEW,A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY),,"vmem","=Os8.new",fSTOREMMV(EA,fNEWVREG(OsN)))
// V65 store relase, zero byte store
// V65 store release, zero byte store
MMVEC_EACH_EA(vS32b_srls,"Aligned Vector Scatter Release",ATTRIBS(ATTR_VMEM,A_STORE,A_CVI_SCATTER_RELEASE,A_CVI_NEW,A_RESTRICT_SLOT0ONLY),,"vmem",":scatter_release",fSTORERELEASE(EA,0))
@ -2045,11 +2045,11 @@ VxV.uw[0] = RtV;)
ITERATOR_INSN_MPY_SLOT_LATE(32,lvsplatw, "Vd32=vsplat(Rt32)", "Replicates scalar accross words in vector", VdV.uw[i] = RtV)
ITERATOR_INSN_MPY_SLOT_LATE(32,lvsplatw, "Vd32=vsplat(Rt32)", "Replicates scalar across words in vector", VdV.uw[i] = RtV)
ITERATOR_INSN_MPY_SLOT_LATE(16,lvsplath, "Vd32.h=vsplat(Rt32)", "Replicates scalar accross halves in vector", VdV.uh[i] = RtV)
ITERATOR_INSN_MPY_SLOT_LATE(16,lvsplath, "Vd32.h=vsplat(Rt32)", "Replicates scalar across halves in vector", VdV.uh[i] = RtV)
ITERATOR_INSN_MPY_SLOT_LATE(8,lvsplatb, "Vd32.b=vsplat(Rt32)", "Replicates scalar accross bytes in vector", VdV.ub[i] = RtV)
ITERATOR_INSN_MPY_SLOT_LATE(8,lvsplatb, "Vd32.b=vsplat(Rt32)", "Replicates scalar across bytes in vector", VdV.ub[i] = RtV)
ITERATOR_INSN_ANY_SLOT(32,vassign,"Vd32=Vu32","Copy a vector",VdV.w[i]=VuV.w[i])

2
tests/tcg/hexagon/fpstuff.c
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@ -52,7 +52,7 @@ static void check_compare_exception(void)
uint32_t cmp;
uint32_t usr;
/* Check that FP compares are quiet (don't raise any execptions) */
/* Check that FP compares are quiet (don't raise any exceptions) */
asm (CLEAR_FPSTATUS
"p0 = sfcmp.eq(%2, %3)\n\t"
"%0 = p0\n\t"

2
tests/tcg/hexagon/test_clobber.S
View File

@ -1,5 +1,5 @@
/*
* Purpose: demonstrate the succesful operation of the register save mechanism,
* Purpose: demonstrate the successful operation of the register save mechanism,
* in which the caller saves the registers that will be clobbered, and restores
* them after the call.
*/