target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed for some security issues. Add the definitions for them to be used by named CPU models. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20191225063018.20038-2-xiaoyao.li@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -835,12 +835,15 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
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/* MSR Feature Bits */
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#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
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#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
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#define MSR_ARCH_CAP_RSBA (1U << 2)
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#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
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#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
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#define MSR_ARCH_CAP_RSBA (1U << 2)
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#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
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#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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#define MSR_ARCH_CAP_MDS_NO (1U << 5)
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#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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#define MSR_ARCH_CAP_MDS_NO (1U << 5)
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#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
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#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
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#define MSR_ARCH_CAP_TAA_NO (1U << 8)
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#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
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