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tcg/arm: Remove use_armv5t_instructions 

This is now always true, since we require armv6.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-01-02 18:30:13 -08:00
parent 01dfc0ed7f
commit 6cef13940c
2 changed files with 7 additions and 31 deletions
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35
tcg/arm/tcg-target.c.inc
View File

@ -596,11 +596,7 @@ static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn)
* Unless the C portion of QEMU is compiled as thumb, we don't need
* true BX semantics; merely a branch to an address held in a register.
*/
if (use_armv5t_instructions) {
tcg_out_bx_reg(s, cond, rn);
} else {
tcg_out_mov_reg(s, cond, TCG_REG_PC, rn);
}
tcg_out_bx_reg(s, cond, rn);
}
static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc,
@ -1247,14 +1243,7 @@ static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr)
}
/* LDR is interworking from v5t. */
if (arm_mode || use_armv5t_instructions) {
tcg_out_movi_pool(s, cond, TCG_REG_PC, addri);
return;
}
/* else v4t */
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP);
tcg_out_movi_pool(s, cond, TCG_REG_PC, addri);
}
/*
@ -1270,26 +1259,14 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr)
if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) {
if (arm_mode) {
tcg_out_bl_imm(s, COND_AL, disp);
return;
}
if (use_armv5t_instructions) {
} else {
tcg_out_blx_imm(s, disp);
return;
}
return;
}
if (use_armv5t_instructions) {
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP);
} else if (arm_mode) {
/* ??? Know that movi_pool emits exactly 1 insn. */
tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC);
tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri);
} else {
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
tcg_out_mov_reg(s, COND_AL, TCG_REG_R14, TCG_REG_PC);
tcg_out_bx_reg(s, COND_AL, TCG_REG_TMP);
}
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP);
}
static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l)

3
tcg/arm/tcg-target.h
View File

@ -28,7 +28,6 @@
extern int arm_arch;
#define use_armv5t_instructions (__ARM_ARCH >= 5 || arm_arch >= 5)
#define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6)
#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
@ -109,7 +108,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_clz_i32 use_armv5t_instructions
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
#define TCG_TARGET_HAS_ctpop_i32 0
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions