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Fix https://bugs.launchpad.net/bugs/1701835

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Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20190519' into staging

Fix https://bugs.launchpad.net/bugs/1701835

# gpg: Signature made Sun 19 May 2019 15:31:37 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-axp-20190519:
  target/alpha: Fix user-only floating-point exceptions
  target/alpha: Clean up alpha_cpu_dump_state

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-05-20 11:38:36 +01:00
commit 6d8e75d41c
5 changed files with 140 additions and 69 deletions
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104
linux-user/syscall.c
View File

@ -10223,18 +10223,11 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
switch (arg1) {
case TARGET_GSI_IEEE_FP_CONTROL:
{
uint64_t swcr, fpcr = cpu_alpha_load_fpcr (cpu_env);
uint64_t fpcr = cpu_alpha_load_fpcr(cpu_env);
uint64_t swcr = ((CPUAlphaState *)cpu_env)->swcr;
/* Copied from linux ieee_fpcr_to_swcr. */
swcr = (fpcr >> 35) & SWCR_STATUS_MASK;
swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
| SWCR_TRAP_ENABLE_DZE
| SWCR_TRAP_ENABLE_OVF);
swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF
| SWCR_TRAP_ENABLE_INE);
swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
swcr &= ~SWCR_STATUS_MASK;
swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
if (put_user_u64 (swcr, arg2))
return -TARGET_EFAULT;
@ -10261,25 +10254,24 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
switch (arg1) {
case TARGET_SSI_IEEE_FP_CONTROL:
{
uint64_t swcr, fpcr, orig_fpcr;
uint64_t swcr, fpcr;
if (get_user_u64 (swcr, arg2)) {
return -TARGET_EFAULT;
}
orig_fpcr = cpu_alpha_load_fpcr(cpu_env);
fpcr = orig_fpcr & FPCR_DYN_MASK;
/* Copied from linux ieee_swcr_to_fpcr. */
fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
| SWCR_TRAP_ENABLE_DZE
| SWCR_TRAP_ENABLE_OVF)) << 48;
fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
| SWCR_TRAP_ENABLE_INE)) << 57;
fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
/*
* The kernel calls swcr_update_status to update the
* status bits from the fpcr at every point that it
* could be queried. Therefore, we store the status
* bits only in FPCR.
*/
((CPUAlphaState *)cpu_env)->swcr
= swcr & (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK);
fpcr = cpu_alpha_load_fpcr(cpu_env);
fpcr &= ((uint64_t)FPCR_DYN_MASK << 32);
fpcr |= alpha_ieee_swcr_to_fpcr(swcr);
cpu_alpha_store_fpcr(cpu_env, fpcr);
ret = 0;
}
@ -10287,44 +10279,47 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
case TARGET_SSI_IEEE_RAISE_EXCEPTION:
{
uint64_t exc, fpcr, orig_fpcr;
int si_code;
uint64_t exc, fpcr, fex;
if (get_user_u64(exc, arg2)) {
return -TARGET_EFAULT;
}
orig_fpcr = cpu_alpha_load_fpcr(cpu_env);
/* We only add to the exception status here. */
fpcr = orig_fpcr | ((exc & SWCR_STATUS_MASK) << 35);
cpu_alpha_store_fpcr(cpu_env, fpcr);
ret = 0;
exc &= SWCR_STATUS_MASK;
fpcr = cpu_alpha_load_fpcr(cpu_env);
/* Old exceptions are not signaled. */
fpcr &= ~(orig_fpcr & FPCR_STATUS_MASK);
fex = alpha_ieee_fpcr_to_swcr(fpcr);
fex = exc & ~fex;
fex >>= SWCR_STATUS_TO_EXCSUM_SHIFT;
fex &= ((CPUArchState *)cpu_env)->swcr;
/* If any exceptions set by this call,
and are unmasked, send a signal. */
si_code = 0;
if ((fpcr & (FPCR_INE | FPCR_INED)) == FPCR_INE) {
si_code = TARGET_FPE_FLTRES;
}
if ((fpcr & (FPCR_UNF | FPCR_UNFD)) == FPCR_UNF) {
si_code = TARGET_FPE_FLTUND;
}
if ((fpcr & (FPCR_OVF | FPCR_OVFD)) == FPCR_OVF) {
si_code = TARGET_FPE_FLTOVF;
}
if ((fpcr & (FPCR_DZE | FPCR_DZED)) == FPCR_DZE) {
si_code = TARGET_FPE_FLTDIV;
}
if ((fpcr & (FPCR_INV | FPCR_INVD)) == FPCR_INV) {
si_code = TARGET_FPE_FLTINV;
}
if (si_code != 0) {
/* Update the hardware fpcr. */
fpcr |= alpha_ieee_swcr_to_fpcr(exc);
cpu_alpha_store_fpcr(cpu_env, fpcr);
if (fex) {
int si_code = TARGET_FPE_FLTUNK;
target_siginfo_t info;
if (fex & SWCR_TRAP_ENABLE_DNO) {
si_code = TARGET_FPE_FLTUND;
}
if (fex & SWCR_TRAP_ENABLE_INE) {
si_code = TARGET_FPE_FLTRES;
}
if (fex & SWCR_TRAP_ENABLE_UNF) {
si_code = TARGET_FPE_FLTUND;
}
if (fex & SWCR_TRAP_ENABLE_OVF) {
si_code = TARGET_FPE_FLTOVF;
}
if (fex & SWCR_TRAP_ENABLE_DZE) {
si_code = TARGET_FPE_FLTDIV;
}
if (fex & SWCR_TRAP_ENABLE_INV) {
si_code = TARGET_FPE_FLTINV;
}
info.si_signo = SIGFPE;
info.si_errno = 0;
info.si_code = si_code;
@ -10333,6 +10328,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
queue_signal((CPUArchState *)cpu_env, info.si_signo,
QEMU_SI_FAULT, &info);
}
ret = 0;
}
break;

3
linux-user/syscall_defs.h
View File

@ -635,7 +635,8 @@ typedef struct target_siginfo {
#define TARGET_FPE_FLTRES (6) /* floating point inexact result */
#define TARGET_FPE_FLTINV (7) /* floating point invalid operation */
#define TARGET_FPE_FLTSUB (8) /* subscript out of range */
#define TARGET_NSIGFPE 8
#define TARGET_FPE_FLTUNK (14) /* undiagnosed fp exception */
#define TARGET_NSIGFPE 15
/*
* SIGSEGV si_codes

42
target/alpha/cpu.h
View File

@ -198,6 +198,8 @@ enum {
#define SWCR_STATUS_DNO (1U << 22)
#define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
#define SWCR_STATUS_TO_EXCSUM_SHIFT 16
#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
/* MMU modes definitions */
@ -235,6 +237,9 @@ struct CPUAlphaState {
/* The FPCR, and disassembled portions thereof. */
uint32_t fpcr;
#ifdef CONFIG_USER_ONLY
uint32_t swcr;
#endif
uint32_t fpcr_exc_enable;
float_status fp_status;
uint8_t fpcr_dyn_round;
@ -501,4 +506,41 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
*pflags = env->flags & ENV_FLAG_TB_MASK;
}
#ifdef CONFIG_USER_ONLY
/* Copied from linux ieee_swcr_to_fpcr. */
static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
{
uint64_t fpcr = 0;
fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
| SWCR_TRAP_ENABLE_DZE
| SWCR_TRAP_ENABLE_OVF)) << 48;
fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
| SWCR_TRAP_ENABLE_INE)) << 57;
fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
return fpcr;
}
/* Copied from linux ieee_fpcr_to_swcr. */
static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr)
{
uint64_t swcr = 0;
swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
| SWCR_TRAP_ENABLE_DZE
| SWCR_TRAP_ENABLE_OVF);
swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE);
swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
return swcr;
}
#endif /* CONFIG_USER_ONLY */
#endif /* ALPHA_CPU_H */

21
target/alpha/fpu_helper.c
View File

@ -91,10 +91,25 @@ void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
if (exc) {
env->fpcr |= exc;
exc &= ~ignore;
if (exc) {
exc &= env->fpcr_exc_enable;
fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC);
#ifdef CONFIG_USER_ONLY
/*
* In user mode, the kernel's software handler only
* delivers a signal if the exception is enabled.
*/
if (!(exc & env->fpcr_exc_enable)) {
return;
}
#else
/*
* In system mode, the software handler gets invoked
* for any non-ignored exception.
*/
if (!exc) {
return;
}
#endif
exc &= env->fpcr_exc_enable;
fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC);
}
}

39
target/alpha/helper.c
View File

@ -29,12 +29,12 @@
#define CONVERT_BIT(X, SRC, DST) \
(SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
uint64_t cpu_alpha_load_fpcr(CPUAlphaState *env)
{
return (uint64_t)env->fpcr << 32;
}
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val)
{
uint32_t fpcr = val >> 32;
uint32_t t = 0;
@ -67,6 +67,22 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ);
env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0;
#ifdef CONFIG_USER_ONLY
/*
* Override some of these bits with the contents of ENV->SWCR.
* In system mode, some of these would trap to the kernel, at
* which point the kernel's handler would emulate and apply
* the software exception mask.
*/
if (env->swcr & SWCR_MAP_DMZ) {
env->fp_status.flush_inputs_to_zero = 1;
}
if (env->swcr & SWCR_MAP_UMZ) {
env->fp_status.flush_to_zero = 1;
}
env->fpcr_exc_enable &= ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32);
#endif
}
uint64_t helper_load_fpcr(CPUAlphaState *env)
@ -435,32 +451,33 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
static const char *linux_reg_names[] = {
"v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
"t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",
"a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
"t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
static const char linux_reg_names[31][4] = {
"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
"t10", "t11", "ra", "t12", "at", "gp", "sp"
};
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
int i;
qemu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n",
qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n",
env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8));
for (i = 0; i < 31; i++) {
qemu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i,
qemu_fprintf(f, "%-8s" TARGET_FMT_lx "%c",
linux_reg_names[i], cpu_alpha_load_gr(env, i),
(i % 3) == 2 ? '\n' : ' ');
}
qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
env->lock_addr, env->lock_value);
if (flags & CPU_DUMP_FPU) {
for (i = 0; i < 31; i++) {
qemu_fprintf(f, "FIR%02d %016" PRIx64 "%c", i, env->fir[i],
qemu_fprintf(f, "f%-7d%016" PRIx64 "%c", i, env->fir[i],
(i % 3) == 2 ? '\n' : ' ');
}
qemu_fprintf(f, "fpcr %016" PRIx64 "\n", cpu_alpha_load_fpcr(env));
}
qemu_fprintf(f, "\n");
}