target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
Implement the SIMD 3-reg-same instructions SQADD, UQADD, SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL, SQRSHL, UQRSHL; these are all simple calls to existing Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL for the 3-reg-same-scalar category (but not the others because they can have non-size-64 operands and the scalar_3reg_same function doesn't support that yet.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Peter Maydell
parent
3ea3bd6245
commit
6d9571f7d8
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@ -74,6 +74,7 @@ typedef struct AArch64DecodeTable {
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/* Function prototype for gen_ functions for calling Neon helpers */
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typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
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typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
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/* initialize TCG globals. */
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void a64_translate_init(void)
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@ -5738,6 +5739,20 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
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TCGCond cond;
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switch (opcode) {
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case 0x1: /* SQADD */
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if (u) {
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gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
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} else {
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gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
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}
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break;
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case 0x5: /* SQSUB */
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if (u) {
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gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
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} else {
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gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
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}
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break;
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case 0x6: /* CMGT, CMHI */
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/* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
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* We implement this using setcond (test) and then negating.
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@ -5760,6 +5775,34 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
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tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0);
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tcg_gen_neg_i64(tcg_rd, tcg_rd);
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break;
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case 0x8: /* SSHL, USHL */
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if (u) {
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gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm);
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} else {
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gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm);
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}
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break;
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case 0x9: /* SQSHL, UQSHL */
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if (u) {
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gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
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} else {
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gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
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}
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break;
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case 0xa: /* SRSHL, URSHL */
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if (u) {
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gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm);
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} else {
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gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm);
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}
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break;
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case 0xb: /* SQRSHL, UQRSHL */
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if (u) {
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gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
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} else {
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gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
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}
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break;
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case 0x10: /* ADD, SUB */
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if (u) {
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tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm);
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@ -5767,12 +5810,6 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
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tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm);
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}
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break;
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case 0x1: /* SQADD */
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case 0x5: /* SQSUB */
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case 0x8: /* SSHL, USHL */
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case 0x9: /* SQSHL, UQSHL */
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case 0xa: /* SRSHL, URSHL */
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case 0xb: /* SQRSHL, UQRSHL */
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default:
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g_assert_not_reached();
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}
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@ -5949,10 +5986,10 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
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switch (opcode) {
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case 0x1: /* SQADD, UQADD */
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case 0x5: /* SQSUB, UQSUB */
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case 0x8: /* SSHL, USHL */
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case 0xa: /* SRSHL, URSHL */
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unsupported_encoding(s, insn);
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return;
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case 0x8: /* SSHL, USHL */
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case 0xa: /* SRSHL, URSHL */
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case 0x6: /* CMGT, CMHI */
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case 0x7: /* CMGE, CMHS */
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case 0x11: /* CMTST, CMEQ */
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@ -6621,18 +6658,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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}
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unsupported_encoding(s, insn);
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return;
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case 0x1: /* SQADD */
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case 0x5: /* SQSUB */
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case 0x8: /* SSHL, USHL */
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case 0x9: /* SQSHL, UQSHL */
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case 0xa: /* SRSHL, URSHL */
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case 0xb: /* SQRSHL, UQRSHL */
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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unsupported_encoding(s, insn);
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return;
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case 0x16: /* SQDMULH, SQRDMULH */
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if (size == 0 || size == 3) {
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unallocated_encoding(s);
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@ -6670,12 +6695,33 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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TCGv_i32 tcg_op1 = tcg_temp_new_i32();
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TCGv_i32 tcg_op2 = tcg_temp_new_i32();
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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NeonGenTwoOpFn *genfn;
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NeonGenTwoOpFn *genfn = NULL;
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NeonGenTwoOpEnvFn *genenvfn = NULL;
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read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
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read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
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switch (opcode) {
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case 0x1: /* SQADD, UQADD */
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{
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static NeonGenTwoOpEnvFn * const fns[3][2] = {
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{ gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
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{ gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
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{ gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
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};
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genenvfn = fns[size][u];
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break;
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}
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case 0x5: /* SQSUB, UQSUB */
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{
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static NeonGenTwoOpEnvFn * const fns[3][2] = {
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{ gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
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{ gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
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{ gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
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};
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genenvfn = fns[size][u];
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break;
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}
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case 0x6: /* CMGT, CMHI */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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@ -6696,6 +6742,46 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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genfn = fns[size][u];
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break;
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}
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case 0x8: /* SSHL, USHL */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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{ gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
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{ gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
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{ gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
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};
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genfn = fns[size][u];
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break;
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}
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case 0x9: /* SQSHL, UQSHL */
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{
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static NeonGenTwoOpEnvFn * const fns[3][2] = {
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{ gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
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{ gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
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{ gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
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};
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genenvfn = fns[size][u];
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break;
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}
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case 0xa: /* SRSHL, URSHL */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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{ gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 },
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{ gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 },
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{ gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 },
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};
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genfn = fns[size][u];
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break;
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}
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case 0xb: /* SQRSHL, UQRSHL */
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{
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static NeonGenTwoOpEnvFn * const fns[3][2] = {
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{ gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
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{ gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
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{ gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
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};
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genenvfn = fns[size][u];
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break;
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}
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case 0x10: /* ADD, SUB */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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@ -6720,7 +6806,11 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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g_assert_not_reached();
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}
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genfn(tcg_res, tcg_op1, tcg_op2);
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if (genenvfn) {
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genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2);
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} else {
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genfn(tcg_res, tcg_op1, tcg_op2);
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}
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write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
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