aspeed/smc: add a 'sdram_base' property
The DRAM address of a DMA transaction depends on the DRAM base address of the SoC. Inform the SMC controller model with this value. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190618165311.27066-15-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -337,6 +337,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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aspeed_soc_get_irq(s, ASPEED_I2C));
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aspeed_soc_get_irq(s, ASPEED_I2C));
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/* FMC, The number of CS is set at the board level */
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/* FMC, The number of CS is set at the board level */
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object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
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"sdram-base", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
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object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
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if (err) {
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if (err) {
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error_propagate(errp, err);
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error_propagate(errp, err);
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@ -913,6 +913,7 @@ static const VMStateDescription vmstate_aspeed_smc = {
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static Property aspeed_smc_properties[] = {
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static Property aspeed_smc_properties[] = {
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DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
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DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
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DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -97,6 +97,9 @@ typedef struct AspeedSMCState {
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uint8_t r_timings;
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uint8_t r_timings;
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uint8_t conf_enable_w0;
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uint8_t conf_enable_w0;
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/* for DMA support */
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uint64_t sdram_base;
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AspeedSMCFlash *flashes;
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AspeedSMCFlash *flashes;
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uint8_t snoop_index;
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uint8_t snoop_index;
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