riscv: Introduce satp mode hw capabilities
Currently, the max satp mode is set with the only constraint that it must be implemented in QEMU, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230303131252.892893-5-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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6df3747a27
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@ -313,17 +313,24 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
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g_assert_not_reached();
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}
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/* Sets the satp mode to the max supported */
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static void set_satp_mode_default_map(RISCVCPU *cpu)
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static void set_satp_mode_max_supported(RISCVCPU *cpu,
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uint8_t satp_mode)
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{
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bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
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const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
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if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) {
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cpu->cfg.satp_mode.map |= (1 << (rv32 ? VM_1_10_SV32 : VM_1_10_SV57));
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} else {
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cpu->cfg.satp_mode.map |= (1 << VM_1_10_MBARE);
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for (int i = 0; i <= satp_mode; ++i) {
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if (valid_vm[i]) {
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cpu->cfg.satp_mode.supported |= (1 << i);
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}
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}
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}
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/* Set the satp mode to the max supported */
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static void set_satp_mode_default_map(RISCVCPU *cpu)
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{
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cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
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}
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#endif
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static void riscv_any_cpu_init(Object *obj)
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@ -334,6 +341,13 @@ static void riscv_any_cpu_init(Object *obj)
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#elif defined(TARGET_RISCV64)
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set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
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#endif
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(RISCV_CPU(obj),
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riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
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VM_1_10_SV32 : VM_1_10_SV57);
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#endif
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set_priv_version(env, PRIV_VERSION_1_12_0);
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register_cpu_props(obj);
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}
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@ -347,6 +361,9 @@ static void rv64_base_cpu_init(Object *obj)
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register_cpu_props(obj);
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/* Set latest version of privileged specification */
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set_priv_version(env, PRIV_VERSION_1_12_0);
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
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#endif
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}
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static void rv64_sifive_u_cpu_init(Object *obj)
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@ -355,6 +372,9 @@ static void rv64_sifive_u_cpu_init(Object *obj)
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set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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register_cpu_props(obj);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
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#endif
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}
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static void rv64_sifive_e_cpu_init(Object *obj)
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@ -366,6 +386,9 @@ static void rv64_sifive_e_cpu_init(Object *obj)
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register_cpu_props(obj);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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cpu->cfg.mmu = false;
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
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#endif
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}
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static void rv64_thead_c906_cpu_init(Object *obj)
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@ -395,6 +418,9 @@ static void rv64_thead_c906_cpu_init(Object *obj)
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cpu->cfg.ext_xtheadsync = true;
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cpu->cfg.mvendorid = THEAD_VENDOR_ID;
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(cpu, VM_1_10_SV39);
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#endif
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}
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static void rv128_base_cpu_init(Object *obj)
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@ -411,6 +437,9 @@ static void rv128_base_cpu_init(Object *obj)
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register_cpu_props(obj);
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/* Set latest version of privileged specification */
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set_priv_version(env, PRIV_VERSION_1_12_0);
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
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#endif
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}
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#else
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static void rv32_base_cpu_init(Object *obj)
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@ -421,6 +450,9 @@ static void rv32_base_cpu_init(Object *obj)
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register_cpu_props(obj);
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/* Set latest version of privileged specification */
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set_priv_version(env, PRIV_VERSION_1_12_0);
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
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#endif
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}
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static void rv32_sifive_u_cpu_init(Object *obj)
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@ -429,6 +461,9 @@ static void rv32_sifive_u_cpu_init(Object *obj)
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set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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register_cpu_props(obj);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
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#endif
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}
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static void rv32_sifive_e_cpu_init(Object *obj)
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@ -440,6 +475,9 @@ static void rv32_sifive_e_cpu_init(Object *obj)
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register_cpu_props(obj);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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cpu->cfg.mmu = false;
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
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#endif
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}
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static void rv32_ibex_cpu_init(Object *obj)
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@ -451,6 +489,9 @@ static void rv32_ibex_cpu_init(Object *obj)
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register_cpu_props(obj);
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set_priv_version(env, PRIV_VERSION_1_11_0);
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cpu->cfg.mmu = false;
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
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#endif
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cpu->cfg.epmp = true;
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}
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@ -463,6 +504,9 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
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register_cpu_props(obj);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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cpu->cfg.mmu = false;
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#ifndef CONFIG_USER_ONLY
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set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
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#endif
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}
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#endif
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@ -999,8 +1043,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
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{
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bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
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const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
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uint8_t satp_mode_max;
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uint8_t satp_mode_map_max;
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uint8_t satp_mode_supported_max =
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satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
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if (cpu->cfg.satp_mode.map == 0) {
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if (cpu->cfg.satp_mode.init == 0) {
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@ -1013,9 +1058,10 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
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* valid_vm_1_10_32/64.
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*/
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for (int i = 1; i < 16; ++i) {
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if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) {
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if ((cpu->cfg.satp_mode.init & (1 << i)) &&
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(cpu->cfg.satp_mode.supported & (1 << i))) {
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for (int j = i - 1; j >= 0; --j) {
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if (valid_vm[j]) {
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if (cpu->cfg.satp_mode.supported & (1 << j)) {
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cpu->cfg.satp_mode.map |= (1 << j);
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break;
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}
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@ -1026,37 +1072,36 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
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}
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}
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/* Make sure the configuration asked is supported by qemu */
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for (int i = 0; i < 16; ++i) {
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if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) {
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error_setg(errp, "satp_mode %s is not valid",
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satp_mode_str(i, rv32));
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return;
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}
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satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
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/* Make sure the user asked for a supported configuration (HW and qemu) */
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if (satp_mode_map_max > satp_mode_supported_max) {
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error_setg(errp, "satp_mode %s is higher than hw max capability %s",
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satp_mode_str(satp_mode_map_max, rv32),
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satp_mode_str(satp_mode_supported_max, rv32));
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return;
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}
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/*
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* Make sure the user did not ask for an invalid configuration as per
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* the specification.
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*/
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satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
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if (!rv32) {
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for (int i = satp_mode_max - 1; i >= 0; --i) {
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for (int i = satp_mode_map_max - 1; i >= 0; --i) {
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if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
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(cpu->cfg.satp_mode.init & (1 << i)) &&
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valid_vm[i]) {
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(cpu->cfg.satp_mode.supported & (1 << i))) {
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error_setg(errp, "cannot disable %s satp mode if %s "
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"is enabled", satp_mode_str(i, false),
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satp_mode_str(satp_mode_max, false));
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satp_mode_str(satp_mode_map_max, false));
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return;
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}
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}
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}
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/* Finally expand the map so that all valid modes are set */
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for (int i = satp_mode_max - 1; i >= 0; --i) {
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if (valid_vm[i]) {
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for (int i = satp_mode_map_max - 1; i >= 0; --i) {
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if (cpu->cfg.satp_mode.supported & (1 << i)) {
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cpu->cfg.satp_mode.map |= (1 << i);
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}
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}
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@ -404,13 +404,17 @@ struct RISCVCPUClass {
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/*
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* map is a 16-bit bitmap: the most significant set bit in map is the maximum
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* satp mode that is supported.
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* satp mode that is supported. It may be chosen by the user and must respect
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* what qemu implements (valid_1_10_32/64) and what the hw is capable of
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* (supported bitmap below).
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*
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* init is a 16-bit bitmap used to make sure the user selected a correct
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* configuration as per the specification.
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*
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* supported is a 16-bit bitmap used to reflect the hw capabilities.
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*/
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typedef struct {
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uint16_t map, init;
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uint16_t map, init, supported;
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} RISCVSATPMap;
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struct RISCVCPUConfig {
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