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target/ppc: Implement lxvkq instruction 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-25-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Matheus Ferst 2021-11-04 09:37:18 -03:00 committed by David Gibson
parent 788c63998c
commit 6e26b85de5
2 changed files with 50 additions and 0 deletions
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7
target/ppc/insn32.decode
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@ -100,6 +100,9 @@
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
&X_uim5 xt uim:uint8_t
@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt=%x_xt
&X_tb_sp_rc rt rb sp rc:bool
@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc
@ -420,3 +423,7 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
## VSX Vector Load Special Value Instruction
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5

43
target/ppc/translate/vsx-impl.c.inc
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@ -1503,6 +1503,49 @@ static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
return true;
}
static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
{
static const uint64_t values[32] = {
0, /* Unspecified */
0x3FFF000000000000llu, /* QP +1.0 */
0x4000000000000000llu, /* QP +2.0 */
0x4000800000000000llu, /* QP +3.0 */
0x4001000000000000llu, /* QP +4.0 */
0x4001400000000000llu, /* QP +5.0 */
0x4001800000000000llu, /* QP +6.0 */
0x4001C00000000000llu, /* QP +7.0 */
0x7FFF000000000000llu, /* QP +Inf */
0x7FFF800000000000llu, /* QP dQNaN */
0, /* Unspecified */
0, /* Unspecified */
0, /* Unspecified */
0, /* Unspecified */
0, /* Unspecified */
0, /* Unspecified */
0x8000000000000000llu, /* QP -0.0 */
0xBFFF000000000000llu, /* QP -1.0 */
0xC000000000000000llu, /* QP -2.0 */
0xC000800000000000llu, /* QP -3.0 */
0xC001000000000000llu, /* QP -4.0 */
0xC001400000000000llu, /* QP -5.0 */
0xC001800000000000llu, /* QP -6.0 */
0xC001C00000000000llu, /* QP -7.0 */
0xFFFF000000000000llu, /* QP -Inf */
};
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VSX(ctx);
if (values[a->uim]) {
set_cpu_vsr(a->xt, tcg_constant_i64(0x0), false);
set_cpu_vsr(a->xt, tcg_constant_i64(values[a->uim]), true);
} else {
gen_invalid(ctx);
}
return true;
}
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;