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target-s390: Convert IPM

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Note that the previous placement of the PM field was incorrect.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2012-09-05 10:18:21 -07:00
parent 8379bfdbca
commit 6e2704e74d
4 changed files with 21 additions and 19 deletions
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12
target-s390x/cc_helper.c
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@ -544,18 +544,6 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src,
return do_calc_cc(env, cc_op, src, dst, vr);
}
/* insert psw mask and condition code into r1 */
void HELPER(ipm)(CPUS390XState *env, uint32_t cc, uint32_t r1)
{
uint64_t r = env->regs[r1];
r &= 0xffffffff00ffffffULL;
r |= (cc << 28) | ((env->psw.mask >> 40) & 0xf);
env->regs[r1] = r;
HELPER_LOG("%s: cc %d psw.mask 0x%lx r1 0x%lx\n", __func__,
cc, env->psw.mask, r);
}
#ifndef CONFIG_USER_ONLY
void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr)
{

1
target-s390x/helper.h
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@ -25,7 +25,6 @@ DEF_HELPER_FLAGS_1(abs_i32, TCG_CALL_NO_RWG_SE, i32, s32)
DEF_HELPER_FLAGS_1(nabs_i32, TCG_CALL_NO_RWG_SE, s32, s32)
DEF_HELPER_FLAGS_1(abs_i64, TCG_CALL_NO_RWG_SE, i64, s64)
DEF_HELPER_FLAGS_1(nabs_i64, TCG_CALL_NO_RWG_SE, s64, s64)
DEF_HELPER_3(ipm, void, env, i32, i32)
DEF_HELPER_4(stam, void, env, i32, i64, i32)
DEF_HELPER_4(lam, void, env, i32, i64, i32)
DEF_HELPER_4(mvcle, i32, env, i32, i64, i32)

2
target-s390x/insn-data.def
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@ -237,6 +237,8 @@
D(0xa501, IIHL, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1020)
D(0xa502, IILH, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1010)
D(0xa503, IILL, RI_a, Z, r1_o, i2_16u, r1, 0, insi, 0, 0x1000)
/* INSERT PROGRAM MASK */
C(0xb222, IPM, RRE, Z, 0, 0, r1, 0, ipm, 0)
/* LOAD */
C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0)

25
target-s390x/translate.c
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@ -1034,12 +1034,6 @@ static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
switch (op) {
case 0x22: /* IPM R1 [RRE] */
tmp32_1 = tcg_const_i32(r1);
gen_op_calc_cc(s);
gen_helper_ipm(cpu_env, cc_op, tmp32_1);
tcg_temp_free_i32(tmp32_1);
break;
case 0x41: /* CKSM R1,R2 [RRE] */
tmp32_1 = tcg_const_i32(r1);
tmp32_2 = tcg_const_i32(r2);
@ -2348,6 +2342,25 @@ static ExitStatus op_insi(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
{
TCGv_i64 t1;
gen_op_calc_cc(s);
tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
t1 = tcg_temp_new_i64();
tcg_gen_shli_i64(t1, psw_mask, 20);
tcg_gen_shri_i64(t1, t1, 36);
tcg_gen_or_i64(o->out, o->out, t1);
tcg_gen_extu_i32_i64(t1, cc_op);
tcg_gen_shli_i64(t1, t1, 28);
tcg_gen_or_i64(o->out, o->out, t1);
tcg_temp_free_i64(t1);
return NO_EXIT;
}
static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
{
gen_helper_ldeb(o->out, cpu_env, o->in2);