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pci: introduce pcibus_t to represent pci bus address/size instead of uint32_t 

This patch is preliminary for 64 bit BAR support.
Introduce dedicated type, pcibus_t, to represent pci bus address/size
instead of uint32_t.
Later this type will be changed to uint64_t.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Isaku Yamahata 2009-10-30 21:21:08 +09:00 committed by Anthony Liguori
parent a455783bb6
commit 6e355d901b
24 changed files with 43 additions and 40 deletions
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2
hw/ac97.c
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@ -1250,7 +1250,7 @@ static int ac97_load (QEMUFile *f, void *opaque, int version_id)
}
static void ac97_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
PCIDevice *d = &s->dev;

4
hw/cirrus_vga.c
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@ -3174,7 +3174,7 @@ void isa_cirrus_vga_init(void)
***************************************/
static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
@ -3195,7 +3195,7 @@ static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
}
static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;

6
hw/e1000.c
View File

@ -145,8 +145,8 @@ static const char phy_regcap[0x20] = {
};
static void
ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
uint32_t size, int type)
ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
pcibus_t size, int type)
{
DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
}
@ -1011,7 +1011,7 @@ static CPUReadMemoryFunc * const e1000_mmio_read[] = {
static void
e1000_mmio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
int i;

4
hw/eepro100.c
View File

@ -1384,7 +1384,7 @@ static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
/* PCI EEPRO100 definitions */
static void pci_map(PCIDevice * pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
@ -1463,7 +1463,7 @@ static CPUReadMemoryFunc * const pci_mmio_read[] = {
};
static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);

2
hw/es1370.c
View File

@ -907,7 +907,7 @@ static void es1370_adc_callback (void *opaque, int avail)
}
static void es1370_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
ES1370State *s = DO_UPCAST (ES1370State, dev, pci_dev);

4
hw/ide/cmd646.c
View File

@ -45,7 +45,7 @@
static void cmd646_update_irq(PCIIDEState *d);
static void ide_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
IDEBus *bus;
@ -136,7 +136,7 @@ static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
}
static void bmdma_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
int i;

2
hw/ide/piix.c
View File

@ -69,7 +69,7 @@ static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
}
static void bmdma_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
int i;

6
hw/lsi53c895a.c
View File

@ -1925,7 +1925,7 @@ static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
}
static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
@ -1940,7 +1940,7 @@ static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
}
static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
@ -1950,7 +1950,7 @@ static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
}
static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);

2
hw/macio.c
View File

@ -40,7 +40,7 @@ struct macio_state_t {
};
static void macio_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
macio_state_t *macio_state;
int i;

2
hw/msix.c
View File

@ -200,7 +200,7 @@ static CPUReadMemoryFunc * const msix_mmio_read[] = {
/* Should be called from device's map method. */
void msix_mmio_map(PCIDevice *d, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
uint8_t *config = d->config + d->msix_cap;
uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);

3
hw/msix.h
View File

@ -2,6 +2,7 @@
#define QEMU_MSIX_H
#include "qemu-common.h"
#include "pci.h"
int msix_init(PCIDevice *pdev, unsigned short nentries,
unsigned bar_nr, unsigned bar_size);
@ -10,7 +11,7 @@ void msix_write_config(PCIDevice *pci_dev, uint32_t address,
uint32_t val, int len);
void msix_mmio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type);
pcibus_t addr, pcibus_t size, int type);
int msix_uninit(PCIDevice *d);

2
hw/ne2000.c
View File

@ -679,7 +679,7 @@ const VMStateDescription vmstate_pci_ne2000 = {
/* PCI NE2000 definitions */
static void ne2000_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
NE2000State *s = &d->ne2000;

2
hw/openpic.c
View File

@ -1026,7 +1026,7 @@ static CPUReadMemoryFunc * const openpic_read[] = {
};
static void openpic_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
openpic_t *opp;

6
hw/pci.c
View File

@ -455,12 +455,12 @@ static int pci_unregister_device(DeviceState *dev)
}
void pci_register_bar(PCIDevice *pci_dev, int region_num,
uint32_t size, int type,
pcibus_t size, int type,
PCIMapIORegionFunc *map_func)
{
PCIIORegion *r;
uint32_t addr;
uint32_t wmask;
pcibus_t wmask;
if ((unsigned int)region_num >= PCI_NUM_REGIONS)
return;
@ -492,7 +492,7 @@ static void pci_update_mappings(PCIDevice *d)
{
PCIIORegion *r;
int cmd, i;
uint32_t last_addr, new_addr;
pcibus_t last_addr, new_addr;
cmd = pci_get_word(d->config + PCI_COMMAND);
for(i = 0; i < PCI_NUM_REGIONS; i++) {

12
hw/pci.h
View File

@ -71,18 +71,20 @@ extern target_phys_addr_t pci_mem_base;
#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
typedef uint32_t pcibus_t;
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
uint32_t address, uint32_t data, int len);
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
uint32_t address, int len);
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type);
pcibus_t addr, pcibus_t size, int type);
typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
typedef struct PCIIORegion {
uint32_t addr; /* current PCI mapping address. -1 means not mapped */
#define PCI_BAR_UNMAPPED (~(uint32_t)0)
uint32_t size;
pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
pcibus_t size;
uint8_t type;
PCIMapIORegionFunc *map_func;
} PCIIORegion;
@ -224,7 +226,7 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name,
PCIConfigWriteFunc *config_write);
void pci_register_bar(PCIDevice *pci_dev, int region_num,
uint32_t size, int type,
pcibus_t size, int type,
PCIMapIORegionFunc *map_func);
int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);

4
hw/pcnet.c
View File

@ -1727,7 +1727,7 @@ static uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
}
static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
PCNetState *d = &DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)->state;
@ -1920,7 +1920,7 @@ static CPUReadMemoryFunc * const pcnet_mmio_read[] = {
};
static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);

4
hw/rtl8139.c
View File

@ -3192,7 +3192,7 @@ static const VMStateDescription vmstate_rtl8139 = {
/* PCI RTL8139 definitions */
static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
@ -3200,7 +3200,7 @@ static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
}
static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);

2
hw/sun4u.c
View File

@ -344,7 +344,7 @@ void cpu_tick_set_limit(void *opaque, uint64_t limit)
}
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
switch (region_num) {

2
hw/usb-ohci.c
View File

@ -1706,7 +1706,7 @@ typedef struct {
} OHCIPCIState;
static void ohci_mapfunc(PCIDevice *pci_dev, int i,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, pci_dev);
cpu_register_physical_memory(addr, size, ohci->state.mem);

2
hw/usb-uhci.c
View File

@ -1047,7 +1047,7 @@ static void uhci_frame_timer(void *opaque)
}
static void uhci_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
UHCIState *s = (UHCIState *)pci_dev;

2
hw/vga-pci.c
View File

@ -48,7 +48,7 @@ static const VMStateDescription vmstate_vga_pci = {
};
static void vga_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
PCIVGAState *d = (PCIVGAState *)pci_dev;
VGACommonState *s = &d->vga;

2
hw/virtio-pci.c
View File

@ -344,7 +344,7 @@ static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val)
}
static void virtio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev);
VirtIODevice *vdev = proxy->vdev;

4
hw/vmware_vga.c
View File

@ -1126,7 +1126,7 @@ static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
}
static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
struct vmsvga_state_s *s = &d->chip;
@ -1146,7 +1146,7 @@ static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
}
static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
struct vmsvga_state_s *s = &d->chip;

2
hw/wdt_i6300esb.c
View File

@ -343,7 +343,7 @@ static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
}
static void i6300esb_map(PCIDevice *dev, int region_num,
uint32_t addr, uint32_t size, int type)
pcibus_t addr, pcibus_t size, int type)
{
static CPUReadMemoryFunc * const mem_read[3] = {
i6300esb_mem_readb,