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unicore32: add target-unicore32 directory for unicore32-linux-user support

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Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Guan Xuetao 2011-04-12 16:25:59 +08:00 committed by Blue Swirl
parent 6d76d23e82
commit 6e64da3cd6
6 changed files with 3142 additions and 0 deletions
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182
target-unicore32/cpu.h Normal file
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/*
* UniCore32 virtual CPU header
*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __CPU_UC32_H__
#define __CPU_UC32_H__
#define TARGET_LONG_BITS 32
#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define ELF_MACHINE EM_UNICORE32
#define CPUState struct CPUState_UniCore32
#include "cpu-defs.h"
#include "softfloat.h"
#define NB_MMU_MODES 2
typedef struct CPUState_UniCore32 {
/* Regs for current mode. */
uint32_t regs[32];
/* Frequently accessed ASR bits are stored separately for efficiently.
This contains all the other bits. Use asr_{read,write} to access
the whole ASR. */
uint32_t uncached_asr;
uint32_t bsr;
/* Banked registers. */
uint32_t banked_bsr[6];
uint32_t banked_r29[6];
uint32_t banked_r30[6];
/* asr flag cache for faster execution */
uint32_t CF; /* 0 or 1 */
uint32_t VF; /* V is the bit 31. All other bits are undefined */
uint32_t NF; /* N is bit 31. All other bits are undefined. */
uint32_t ZF; /* Z set if zero. */
/* System control coprocessor (cp0) */
struct {
uint32_t c0_cpuid;
uint32_t c0_cachetype;
uint32_t c1_sys; /* System control register. */
uint32_t c2_base; /* MMU translation table base. */
uint32_t c3_faultstatus; /* Fault status registers. */
uint32_t c4_faultaddr; /* Fault address registers. */
uint32_t c5_cacheop; /* Cache operation registers. */
uint32_t c6_tlbop; /* TLB operation registers. */
} cp0;
/* UniCore-F64 coprocessor state. */
struct {
float64 regs[16];
uint32_t xregs[32];
float_status fp_status;
} ucf64;
CPU_COMMON
/* Internal CPU feature flags. */
uint32_t features;
} CPUState_UniCore32;
#define ASR_M (0x1f)
#define ASR_MODE_USER (0x10)
#define ASR_MODE_INTR (0x12)
#define ASR_MODE_PRIV (0x13)
#define ASR_MODE_TRAP (0x17)
#define ASR_MODE_EXTN (0x1b)
#define ASR_MODE_SUSR (0x1f)
#define ASR_I (1 << 7)
#define ASR_V (1 << 28)
#define ASR_C (1 << 29)
#define ASR_Z (1 << 30)
#define ASR_N (1 << 31)
#define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
#define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
#define UC32_EXCP_PRIV (ASR_MODE_PRIV)
#define UC32_EXCP_TRAP (ASR_MODE_TRAP)
/* Return the current ASR value. */
target_ulong cpu_asr_read(CPUState *env1);
/* Set the ASR. Note that some bits of mask must be all-set or all-clear. */
void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask);
/* UniCore-F64 system registers. */
#define UC32_UCF64_FPSCR (31)
#define UCF64_FPSCR_MASK (0x27ffffff)
#define UCF64_FPSCR_RND_MASK (0x7)
#define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
#define UCF64_FPSCR_TRAPEN_MASK (0x7f)
#define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
#define UCF64_FPSCR_FLAG_MASK (0x3ff)
#define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
#define UCF64_FPSCR_FLAG_ZERO (1 << 17)
#define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
#define UCF64_FPSCR_FLAG_INVALID (1 << 19)
#define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
#define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
#define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
#define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
#define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
#define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
#define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
#define UC32_HWCAP_CMOV 4 /* 1 << 2 */
#define UC32_HWCAP_UCF64 8 /* 1 << 3 */
#define UC32_CPUID(env) (env->cp0.c0_cpuid)
#define UC32_CPUID_UCV2 0x40010863
#define UC32_CPUID_ANY 0xffffffff
#define cpu_init uc32_cpu_init
#define cpu_exec uc32_cpu_exec
#define cpu_signal_handler uc32_cpu_signal_handler
#define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault
CPUState *uc32_cpu_init(const char *cpu_model);
int uc32_cpu_exec(CPUState *s);
int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmuu);
#define CPU_SAVE_VERSION 2
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index(CPUState *env)
{
return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
}
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
if (newsp) {
env->regs[29] = newsp;
}
env->regs[0] = 0;
}
static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
{
env->regs[16] = newtls;
}
#include "cpu-all.h"
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->regs[31] = tb->pc;
}
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->regs[31];
*cs_base = 0;
*flags = 0;
if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
*flags |= (1 << 6);
}
}
void uc32_translate_init(void);
void do_interrupt(CPUState *);
void switch_mode(CPUState_UniCore32 *, int);
#endif /* __CPU_UC32_H__ */

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/*
* UniCore32 execution defines
*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __UC32_EXEC_H__
#define __UC32_EXEC_H__
#include "config.h"
#include "dyngen-exec.h"
register struct CPUState_UniCore32 *env asm(AREG0);
#include "cpu.h"
#include "exec-all.h"
static inline void env_to_regs(void)
{
}
static inline void regs_to_env(void)
{
}
static inline int cpu_has_work(CPUState *env)
{
return env->interrupt_request &
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
static inline int cpu_halted(CPUState *env)
{
if (!env->halted) {
return 0;
}
/* An interrupt wakes the CPU even if the I and R ASR bits are
set. We use EXITTB to silently wake CPU without causing an
actual interrupt. */
if (cpu_has_work(env)) {
env->halted = 0;
return 0;
}
return EXCP_HALTED;
}
#endif /* __UC32_EXEC_H__ */

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/*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "cpu.h"
#include "exec-all.h"
#include "gdbstub.h"
#include "helper.h"
#include "qemu-common.h"
#include "host-utils.h"
static inline void set_feature(CPUState *env, int feature)
{
env->features |= feature;
}
struct uc32_cpu_t {
uint32_t id;
const char *name;
};
static const struct uc32_cpu_t uc32_cpu_names[] = {
{ UC32_CPUID_UCV2, "UniCore-II"},
{ UC32_CPUID_ANY, "any"},
{ 0, NULL}
};
/* return 0 if not found */
static uint32_t uc32_cpu_find_by_name(const char *name)
{
int i;
uint32_t id;
id = 0;
for (i = 0; uc32_cpu_names[i].name; i++) {
if (strcmp(name, uc32_cpu_names[i].name) == 0) {
id = uc32_cpu_names[i].id;
break;
}
}
return id;
}
CPUState *uc32_cpu_init(const char *cpu_model)
{
CPUState *env;
uint32_t id;
static int inited = 1;
env = qemu_mallocz(sizeof(CPUState));
cpu_exec_init(env);
id = uc32_cpu_find_by_name(cpu_model);
switch (id) {
case UC32_CPUID_UCV2:
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
env->cp0.c0_cachetype = 0x1dd20d2;
env->cp0.c1_sys = 0x00090078;
break;
case UC32_CPUID_ANY: /* For userspace emulation. */
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
}
env->cpu_model_str = cpu_model;
env->cp0.c0_cpuid = id;
env->uncached_asr = ASR_MODE_USER;
env->regs[31] = 0;
if (inited) {
inited = 0;
uc32_translate_init();
}
tlb_flush(env, 1);
qemu_init_vcpu(env);
return env;
}
uint32_t HELPER(clo)(uint32_t x)
{
return clo32(x);
}
uint32_t HELPER(clz)(uint32_t x)
{
return clz32(x);
}
void do_interrupt(CPUState *env)
{
env->exception_index = -1;
}
int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
{
env->exception_index = UC32_EXCP_TRAP;
env->cp0.c4_faultaddr = address;
return 1;
}
/* These should probably raise undefined insn exceptions. */
void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
{
int op1 = (insn >> 8) & 0xf;
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
return;
}
uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
{
int op1 = (insn >> 8) & 0xf;
cpu_abort(env, "cp%i insn %08x\n", op1, insn);
return 0;
}
void HELPER(set_cp0)(CPUState *env, uint32_t insn, uint32_t val)
{
cpu_abort(env, "cp0 insn %08x\n", insn);
}
uint32_t HELPER(get_cp0)(CPUState *env, uint32_t insn)
{
cpu_abort(env, "cp0 insn %08x\n", insn);
return 0;
}
void switch_mode(CPUState *env, int mode)
{
if (mode != ASR_MODE_USER) {
cpu_abort(env, "Tried to switch out of user mode\n");
}
}
void HELPER(set_r29_banked)(CPUState *env, uint32_t mode, uint32_t val)
{
cpu_abort(env, "banked r29 write\n");
}
uint32_t HELPER(get_r29_banked)(CPUState *env, uint32_t mode)
{
cpu_abort(env, "banked r29 read\n");
return 0;
}
/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
Single precition routines have a "s" suffix, double precision a
"d" suffix. */
/* Convert host exception flags to f64 form. */
static inline int ucf64_exceptbits_from_host(int host_bits)
{
int target_bits = 0;
if (host_bits & float_flag_invalid) {
target_bits |= UCF64_FPSCR_FLAG_INVALID;
}
if (host_bits & float_flag_divbyzero) {
target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
}
if (host_bits & float_flag_overflow) {
target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
}
if (host_bits & float_flag_underflow) {
target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
}
if (host_bits & float_flag_inexact) {
target_bits |= UCF64_FPSCR_FLAG_INEXACT;
}
return target_bits;
}
uint32_t HELPER(ucf64_get_fpscr)(CPUState *env)
{
int i;
uint32_t fpscr;
fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
i = get_float_exception_flags(&env->ucf64.fp_status);
fpscr |= ucf64_exceptbits_from_host(i);
return fpscr;
}
/* Convert ucf64 exception flags to target form. */
static inline int ucf64_exceptbits_to_host(int target_bits)
{
int host_bits = 0;
if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
host_bits |= float_flag_invalid;
}
if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
host_bits |= float_flag_divbyzero;
}
if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
host_bits |= float_flag_overflow;
}
if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
host_bits |= float_flag_underflow;
}
if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
host_bits |= float_flag_inexact;
}
return host_bits;
}
void HELPER(ucf64_set_fpscr)(CPUState *env, uint32_t val)
{
int i;
uint32_t changed;
changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
changed ^= val;
if (changed & (UCF64_FPSCR_RND_MASK)) {
i = UCF64_FPSCR_RND(val);
switch (i) {
case 0:
i = float_round_nearest_even;
break;
case 1:
i = float_round_to_zero;
break;
case 2:
i = float_round_up;
break;
case 3:
i = float_round_down;
break;
default: /* 100 and 101 not implement */
cpu_abort(env, "Unsupported UniCore-F64 round mode");
}
set_float_rounding_mode(i, &env->ucf64.fp_status);
}
i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
set_float_exception_flags(i, &env->ucf64.fp_status);
}
float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUState *env)
{
return float32_add(a, b, &env->ucf64.fp_status);
}
float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUState *env)
{
return float64_add(a, b, &env->ucf64.fp_status);
}
float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUState *env)
{
return float32_sub(a, b, &env->ucf64.fp_status);
}
float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUState *env)
{
return float64_sub(a, b, &env->ucf64.fp_status);
}
float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUState *env)
{
return float32_mul(a, b, &env->ucf64.fp_status);
}
float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUState *env)
{
return float64_mul(a, b, &env->ucf64.fp_status);
}
float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUState *env)
{
return float32_div(a, b, &env->ucf64.fp_status);
}
float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUState *env)
{
return float64_div(a, b, &env->ucf64.fp_status);
}
float32 HELPER(ucf64_negs)(float32 a)
{
return float32_chs(a);
}
float64 HELPER(ucf64_negd)(float64 a)
{
return float64_chs(a);
}
float32 HELPER(ucf64_abss)(float32 a)
{
return float32_abs(a);
}
float64 HELPER(ucf64_absd)(float64 a)
{
return float64_abs(a);
}
/* XXX: check quiet/signaling case */
void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUState *env)
{
int flag;
flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
env->CF = 0;
switch (c & 0x7) {
case 0: /* F */
break;
case 1: /* UN */
if (flag == 2) {
env->CF = 1;
}
break;
case 2: /* EQ */
if (flag == 0) {
env->CF = 1;
}
break;
case 3: /* UEQ */
if ((flag == 0) || (flag == 2)) {
env->CF = 1;
}
break;
case 4: /* OLT */
if (flag == -1) {
env->CF = 1;
}
break;
case 5: /* ULT */
if ((flag == -1) || (flag == 2)) {
env->CF = 1;
}
break;
case 6: /* OLE */
if ((flag == -1) || (flag == 0)) {
env->CF = 1;
}
break;
case 7: /* ULE */
if (flag != 1) {
env->CF = 1;
}
break;
}
env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
}
void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUState *env)
{
int flag;
flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
env->CF = 0;
switch (c & 0x7) {
case 0: /* F */
break;
case 1: /* UN */
if (flag == 2) {
env->CF = 1;
}
break;
case 2: /* EQ */
if (flag == 0) {
env->CF = 1;
}
break;
case 3: /* UEQ */
if ((flag == 0) || (flag == 2)) {
env->CF = 1;
}
break;
case 4: /* OLT */
if (flag == -1) {
env->CF = 1;
}
break;
case 5: /* ULT */
if ((flag == -1) || (flag == 2)) {
env->CF = 1;
}
break;
case 6: /* OLE */
if ((flag == -1) || (flag == 0)) {
env->CF = 1;
}
break;
case 7: /* ULE */
if (flag != 1) {
env->CF = 1;
}
break;
}
env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
| (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
}
/* Helper routines to perform bitwise copies between float and int. */
static inline float32 ucf64_itos(uint32_t i)
{
union {
uint32_t i;
float32 s;
} v;
v.i = i;
return v.s;
}
static inline uint32_t ucf64_stoi(float32 s)
{
union {
uint32_t i;
float32 s;
} v;
v.s = s;
return v.i;
}
static inline float64 ucf64_itod(uint64_t i)
{
union {
uint64_t i;
float64 d;
} v;
v.i = i;
return v.d;
}
static inline uint64_t ucf64_dtoi(float64 d)
{
union {
uint64_t i;
float64 d;
} v;
v.d = d;
return v.i;
}
/* Integer to float conversion. */
float32 HELPER(ucf64_si2sf)(float32 x, CPUState *env)
{
return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
}
float64 HELPER(ucf64_si2df)(float32 x, CPUState *env)
{
return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
}
/* Float to integer conversion. */
float32 HELPER(ucf64_sf2si)(float32 x, CPUState *env)
{
return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
}
float32 HELPER(ucf64_df2si)(float64 x, CPUState *env)
{
return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
}
/* floating point conversion */
float64 HELPER(ucf64_sf2df)(float32 x, CPUState *env)
{
return float32_to_float64(x, &env->ucf64.fp_status);
}
float32 HELPER(ucf64_df2sf)(float64 x, CPUState *env)
{
return float64_to_float32(x, &env->ucf64.fp_status);
}

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/*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "def-helper.h"
DEF_HELPER_1(clz, i32, i32)
DEF_HELPER_1(clo, i32, i32)
DEF_HELPER_1(exception, void, i32)
DEF_HELPER_2(asr_write, void, i32, i32)
DEF_HELPER_0(asr_read, i32)
DEF_HELPER_3(set_cp0, void, env, i32, i32)
DEF_HELPER_2(get_cp0, i32, env, i32)
DEF_HELPER_3(set_cp, void, env, i32, i32)
DEF_HELPER_2(get_cp, i32, env, i32)
DEF_HELPER_1(get_user_reg, i32, i32)
DEF_HELPER_2(set_user_reg, void, i32, i32)
DEF_HELPER_2(add_cc, i32, i32, i32)
DEF_HELPER_2(adc_cc, i32, i32, i32)
DEF_HELPER_2(sub_cc, i32, i32, i32)
DEF_HELPER_2(sbc_cc, i32, i32, i32)
DEF_HELPER_2(shl, i32, i32, i32)
DEF_HELPER_2(shr, i32, i32, i32)
DEF_HELPER_2(sar, i32, i32, i32)
DEF_HELPER_2(shl_cc, i32, i32, i32)
DEF_HELPER_2(shr_cc, i32, i32, i32)
DEF_HELPER_2(sar_cc, i32, i32, i32)
DEF_HELPER_2(ror_cc, i32, i32, i32)
DEF_HELPER_2(get_r29_banked, i32, env, i32)
DEF_HELPER_3(set_r29_banked, void, env, i32, i32)
DEF_HELPER_1(ucf64_get_fpscr, i32, env)
DEF_HELPER_2(ucf64_set_fpscr, void, env, i32)
DEF_HELPER_3(ucf64_adds, f32, f32, f32, env)
DEF_HELPER_3(ucf64_addd, f64, f64, f64, env)
DEF_HELPER_3(ucf64_subs, f32, f32, f32, env)
DEF_HELPER_3(ucf64_subd, f64, f64, f64, env)
DEF_HELPER_3(ucf64_muls, f32, f32, f32, env)
DEF_HELPER_3(ucf64_muld, f64, f64, f64, env)
DEF_HELPER_3(ucf64_divs, f32, f32, f32, env)
DEF_HELPER_3(ucf64_divd, f64, f64, f64, env)
DEF_HELPER_1(ucf64_negs, f32, f32)
DEF_HELPER_1(ucf64_negd, f64, f64)
DEF_HELPER_1(ucf64_abss, f32, f32)
DEF_HELPER_1(ucf64_absd, f64, f64)
DEF_HELPER_4(ucf64_cmps, void, f32, f32, i32, env)
DEF_HELPER_4(ucf64_cmpd, void, f64, f64, i32, env)
DEF_HELPER_2(ucf64_sf2df, f64, f32, env)
DEF_HELPER_2(ucf64_df2sf, f32, f64, env)
DEF_HELPER_2(ucf64_si2sf, f32, f32, env)
DEF_HELPER_2(ucf64_si2df, f64, f32, env)
DEF_HELPER_2(ucf64_sf2si, f32, f32, env)
DEF_HELPER_2(ucf64_df2si, f32, f64, env)
#include "def-helper.h"

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/*
* UniCore32 helper routines
*
* Copyright (C) 2010-2011 GUAN Xue-tao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exec.h"
#include "helper.h"
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
void HELPER(exception)(uint32_t excp)
{
env->exception_index = excp;
cpu_loop_exit();
}
static target_ulong asr_read(void)
{
int ZF;
ZF = (env->ZF == 0);
return env->uncached_asr | (env->NF & 0x80000000) | (ZF << 30) |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3);
}
target_ulong cpu_asr_read(CPUState *env1)
{
CPUState *saved_env;
target_ulong ret;
saved_env = env;
env = env1;
ret = asr_read();
env = saved_env;
return ret;
}
target_ulong HELPER(asr_read)(void)
{
return asr_read();
}
static void asr_write(target_ulong val, target_ulong mask)
{
if (mask & ASR_NZCV) {
env->ZF = (~val) & ASR_Z;
env->NF = val;
env->CF = (val >> 29) & 1;
env->VF = (val << 3) & 0x80000000;
}
if ((env->uncached_asr ^ val) & mask & ASR_M) {
switch_mode(env, val & ASR_M);
}
mask &= ~ASR_NZCV;
env->uncached_asr = (env->uncached_asr & ~mask) | (val & mask);
}
void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask)
{
CPUState *saved_env;
saved_env = env;
env = env1;
asr_write(val, mask);
env = saved_env;
}
void HELPER(asr_write)(target_ulong val, target_ulong mask)
{
asr_write(val, mask);
}
/* Access to user mode registers from privileged modes. */
uint32_t HELPER(get_user_reg)(uint32_t regno)
{
uint32_t val;
if (regno == 29) {
val = env->banked_r29[0];
} else if (regno == 30) {
val = env->banked_r30[0];
} else {
val = env->regs[regno];
}
return val;
}
void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
{
if (regno == 29) {
env->banked_r29[0] = val;
} else if (regno == 30) {
env->banked_r30[0] = val;
} else {
env->regs[regno] = val;
}
}
/* ??? Flag setting arithmetic is awkward because we need to do comparisons.
The only way to do that in TCG is a conditional branch, which clobbers
all our temporaries. For now implement these as helper functions. */
uint32_t HELPER(add_cc)(uint32_t a, uint32_t b)
{
uint32_t result;
result = a + b;
env->NF = env->ZF = result;
env->CF = result < a;
env->VF = (a ^ b ^ -1) & (a ^ result);
return result;
}
uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
{
uint32_t result;
if (!env->CF) {
result = a + b;
env->CF = result < a;
} else {
result = a + b + 1;
env->CF = result <= a;
}
env->VF = (a ^ b ^ -1) & (a ^ result);
env->NF = env->ZF = result;
return result;
}
uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
{
uint32_t result;
result = a - b;
env->NF = env->ZF = result;
env->CF = a >= b;
env->VF = (a ^ b) & (a ^ result);
return result;
}
uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
{
uint32_t result;
if (!env->CF) {
result = a - b - 1;
env->CF = a > b;
} else {
result = a - b;
env->CF = a >= b;
}
env->VF = (a ^ b) & (a ^ result);
env->NF = env->ZF = result;
return result;
}
/* Similarly for variable shift instructions. */
uint32_t HELPER(shl)(uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
return 0;
}
return x << shift;
}
uint32_t HELPER(shr)(uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
return 0;
}
return (uint32_t)x >> shift;
}
uint32_t HELPER(sar)(uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
shift = 31;
}
return (int32_t)x >> shift;
}
uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
if (shift == 32) {
env->CF = x & 1;
} else {
env->CF = 0;
}
return 0;
} else if (shift != 0) {
env->CF = (x >> (32 - shift)) & 1;
return x << shift;
}
return x;
}
uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
if (shift == 32) {
env->CF = (x >> 31) & 1;
} else {
env->CF = 0;
}
return 0;
} else if (shift != 0) {
env->CF = (x >> (shift - 1)) & 1;
return x >> shift;
}
return x;
}
uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
{
int shift = i & 0xff;
if (shift >= 32) {
env->CF = (x >> 31) & 1;
return (int32_t)x >> 31;
} else if (shift != 0) {
env->CF = (x >> (shift - 1)) & 1;
return (int32_t)x >> shift;
}
return x;
}
uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
{
int shift1, shift;
shift1 = i & 0xff;
shift = shift1 & 0x1f;
if (shift == 0) {
if (shift1 != 0) {
env->CF = (x >> 31) & 1;
}
return x;
} else {
env->CF = (x >> (shift - 1)) & 1;
return ((uint32_t)x >> shift) | (x << (32 - shift));
}
}

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