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target/arm: Implement writing to CONTROL_NS for v8M

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In commit 50f11062d4 we added support for MSR/MRS access
to the NS banked special registers, but we forgot to implement
the support for writing to CONTROL_NS. Correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-8-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2018-02-15 18:29:37 +00:00
parent 24ac0fb129
commit 6eb3a64e2a
1 changed files with 10 additions and 0 deletions
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10
target/arm/helper.c
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@ -10507,6 +10507,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
} }
env->v7m.faultmask[M_REG_NS] = val & 1; env->v7m.faultmask[M_REG_NS] = val & 1;
return; return;
case 0x94: /* CONTROL_NS */
if (!env->v7m.secure) {
return;
}
write_v7m_control_spsel_for_secstate(env,
val & R_V7M_CONTROL_SPSEL_MASK,
M_REG_NS);
env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
return;
case 0x98: /* SP_NS */ case 0x98: /* SP_NS */
{ {
/* This gives the non-secure SP selected based on whether we're /* This gives the non-secure SP selected based on whether we're