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target/arm: Implement SVE2 scatter store insns 

Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal
store insns.

64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)

32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-45-richard.henderson@linaro.org
Message-Id: <20200422141553.8037-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Stephen Long 2021-05-24 18:03:10 -07:00 committed by Peter Maydell
parent e6eba6e532
commit 6ebca45faf
2 changed files with 18 additions and 0 deletions
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10
target/arm/sve.decode
View File

@ -1388,3 +1388,13 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm
CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx
SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
### SVE2 Memory Store Group
# SVE2 64-bit scatter non-temporal store (vector plus scalar)
STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
@rprr_scatter_store xs=2 esz=3 scale=0
# SVE2 32-bit scatter non-temporal store (vector plus scalar)
STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
@rprr_scatter_store xs=0 esz=2 scale=0

8
target/arm/translate-sve.c
View File

@ -6167,6 +6167,14 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
return true;
}
static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
{
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
return trans_ST1_zprz(s, a);
}
/*
* Prefetches
*/