MIPS patches 2016-01-25
Changes: * fixes and includes clean-up -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJWpesPAAoJEFIRjjwLKdpr+NkH/if/4m1NlzH+Oa1FB5ndd8V/ 0C5Mln4UykqPItXa/iBb0CLliz70OcDCzjdMiH/2sqsLdgNo3uPxm6ielGDg0sqK m3kD0QaYjmZp1F9rxRCqXkaUkyYy3ORMFxD1nVjFisUyySghYSnxEOAmrYu6qnZQ HsBlQp8RXSX3CodkzklG5U61GFGiuXbeQFp+C/LdpEEYk33QI5JyF4xUZXOSo7GC vCoQOFN/xTs/QvB1pICDB9/lGIrLpYxXM+FWlzthmLS0kQUKmCvhAP+wF89cIymN HU+sWhUjEQm1uT++5IadFqsvrog5O7Sm6lUjQoBk/ioNetPrxS8VVFMTokddEN0= =0KqT -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160125' into staging MIPS patches 2016-01-25 Changes: * fixes and includes clean-up # gpg: Signature made Mon 25 Jan 2016 09:29:51 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20160125: mips: Clean up includes target-mips: Fix ALIGN instruction when bp=0 target-mips: silence NaNs for cvt.s.d and cvt.d.s target-mips/cpu.h: Fix spell error Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
6ee06cc3dc
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@ -19,6 +19,7 @@ GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#include "qemu/osdep.h"
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#include "disas/bfd.h"
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/* mips.h. Mips opcode list for GDB, the GNU debugger.
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@ -20,6 +20,7 @@
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/mips/cpudevs.h"
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@ -20,6 +20,7 @@
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/mips/cpudevs.h"
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#include "qemu/timer.h"
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@ -22,6 +22,7 @@
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/mips/mips.h"
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#include "hw/pci/pci.h"
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@ -18,6 +18,7 @@
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* http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/char/serial.h"
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@ -20,6 +20,7 @@
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/mips/cpudevs.h"
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#include "cpu.h"
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@ -22,6 +22,7 @@
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/cpudevs.h"
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@ -22,6 +22,7 @@
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/char/serial.h"
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@ -24,6 +24,7 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/cpudevs.h"
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@ -7,6 +7,7 @@
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* All peripherial devices are attached to this "bus" with
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* the standard PC ISA addresses.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/cpudevs.h"
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@ -18,6 +18,7 @@
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "kvm_mips.h"
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#include "qemu-common.h"
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@ -358,7 +358,7 @@ struct CPUMIPSState {
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#define CP0St_IE 0
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int32_t CP0_IntCtl;
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#define CP0IntCtl_IPTI 29
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#define CP0IntCtl_IPPC1 26
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#define CP0IntCtl_IPPCI 26
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#define CP0IntCtl_VS 5
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int32_t CP0_SRSCtl;
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#define CP0SRSCtl_HSS 26
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@ -17,6 +17,7 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "qemu/bitops.h"
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@ -17,7 +17,7 @@
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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@ -16,11 +16,7 @@
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "sysemu/kvm.h"
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@ -9,7 +9,7 @@
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <sys/types.h>
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#include "qemu/osdep.h"
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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@ -17,6 +17,7 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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@ -1,3 +1,4 @@
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "cpu.h"
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@ -17,7 +17,7 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <sys/stat.h>
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/softmmu-semi.h"
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@ -17,6 +17,7 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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@ -16,7 +16,7 @@
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h>
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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uint64_t fdt2;
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fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
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fdt2 = float64_maybe_silence_nan(fdt2);
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update_fcr31(env, GETPC());
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return fdt2;
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}
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uint32_t fst2;
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fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
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fst2 = float32_maybe_silence_nan(fst2);
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update_fcr31(env, GETPC());
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return fst2;
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}
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@ -21,6 +21,7 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "disas/disas.h"
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#include "tcg-op.h"
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t0 = tcg_temp_new();
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gen_load_gpr(t0, rt);
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if (bp == 0) {
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tcg_gen_mov_tl(cpu_gpr[rd], t0);
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switch (opc) {
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case OPC_ALIGN:
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tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DALIGN:
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tcg_gen_mov_tl(cpu_gpr[rd], t0);
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break;
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#endif
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}
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} else {
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TCGv t1 = tcg_temp_new();
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gen_load_gpr(t1, rs);
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