target/openrisc: Represent MACHI:MACLO as a single unit
Significantly simplifies the implementation of the use of MAC. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
24fc5c0feb
commit
6f7332ba71
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@ -277,8 +277,7 @@ typedef struct CPUOpenRISCState {
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target_ulong ppc; /* Prev PC */
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target_ulong jmp_pc; /* Jump PC */
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target_ulong machi; /* Multiply register MACHI */
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target_ulong maclo; /* Multiply register MACLO */
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uint64_t mac; /* Multiply registers MACHI:MACLO */
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target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */
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target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */
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@ -47,8 +47,8 @@ static const VMStateInfo vmstate_sr = {
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static const VMStateDescription vmstate_env = {
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.name = "env",
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.version_id = 2,
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.minimum_version_id = 2,
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32),
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VMSTATE_UINTTL(pc, CPUOpenRISCState),
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@ -82,6 +82,7 @@ static const VMStateDescription vmstate_env = {
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VMSTATE_UINT32(immucfgr, CPUOpenRISCState),
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VMSTATE_UINT32(esr, CPUOpenRISCState),
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VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
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VMSTATE_UINT64(mac, CPUOpenRISCState),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -120,6 +120,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
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case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
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case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
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break;
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case TO_SPR(5, 1): /* MACLO */
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env->mac = deposit64(env->mac, 0, 32, rb);
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break;
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case TO_SPR(5, 2): /* MACHI */
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env->mac = deposit64(env->mac, 32, 32, rb);
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break;
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case TO_SPR(9, 0): /* PICMR */
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env->picmr |= rb;
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break;
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@ -245,6 +251,13 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
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case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
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break;
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case TO_SPR(5, 1): /* MACLO */
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return (uint32_t)env->mac;
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break;
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case TO_SPR(5, 2): /* MACHI */
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return env->mac >> 32;
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break;
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case TO_SPR(9, 0): /* PICMR */
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return env->picmr;
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@ -60,7 +60,7 @@ static TCGv cpu_sr_ov; /* signed overflow */
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static TCGv cpu_lock_addr;
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static TCGv cpu_lock_value;
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static TCGv_i32 fpcsr;
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static TCGv machi, maclo;
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static TCGv_i64 cpu_mac; /* MACHI:MACLO */
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static TCGv fpmaddhi, fpmaddlo;
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static TCGv_i32 env_flags;
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#include "exec/gen-icount.h"
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@ -105,12 +105,9 @@ void openrisc_translate_init(void)
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fpcsr = tcg_global_mem_new_i32(cpu_env,
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offsetof(CPUOpenRISCState, fpcsr),
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"fpcsr");
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machi = tcg_global_mem_new(cpu_env,
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offsetof(CPUOpenRISCState, machi),
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"machi");
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maclo = tcg_global_mem_new(cpu_env,
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offsetof(CPUOpenRISCState, maclo),
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"maclo");
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cpu_mac = tcg_global_mem_new_i64(cpu_env,
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offsetof(CPUOpenRISCState, mac),
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"mac");
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fpmaddhi = tcg_global_mem_new(cpu_env,
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offsetof(CPUOpenRISCState, fpmaddhi),
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"fpmaddhi");
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@ -365,6 +362,58 @@ static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
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gen_ove_cy(dc);
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}
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static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb)
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{
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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tcg_gen_ext_tl_i64(t1, srca);
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tcg_gen_ext_tl_i64(t2, srcb);
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tcg_gen_mul_i64(t1, t1, t2);
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/* Note that overflow is only computed during addition stage. */
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tcg_gen_xor_i64(t2, cpu_mac, t1);
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tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
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tcg_gen_xor_i64(t1, t1, cpu_mac);
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tcg_gen_andc_i64(t1, t1, t2);
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tcg_temp_free_i64(t2);
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#if TARGET_LONG_BITS == 32
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tcg_gen_extrh_i64_i32(cpu_sr_ov, t1);
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#else
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tcg_gen_mov_i64(cpu_sr_ov, t1);
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#endif
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tcg_temp_free_i64(t1);
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gen_ove_ov(dc);
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}
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static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb)
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{
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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tcg_gen_ext_tl_i64(t1, srca);
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tcg_gen_ext_tl_i64(t2, srcb);
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tcg_gen_mul_i64(t1, t1, t2);
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/* Note that overflow is only computed during subtraction stage. */
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tcg_gen_xor_i64(t2, cpu_mac, t1);
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tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
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tcg_gen_xor_i64(t1, t1, cpu_mac);
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tcg_gen_and_i64(t1, t1, t2);
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tcg_temp_free_i64(t2);
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#if TARGET_LONG_BITS == 32
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tcg_gen_extrh_i64_i32(cpu_sr_ov, t1);
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#else
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tcg_gen_mov_i64(cpu_sr_ov, t1);
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#endif
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tcg_temp_free_i64(t1);
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gen_ove_ov(dc);
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}
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static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs)
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{
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TCGv ea = tcg_temp_new();
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@ -628,23 +677,9 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
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case 0x13: /* l.maci */
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LOG_DIS("l.maci r%d, %d\n", ra, I16);
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{
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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TCGv_i32 dst = tcg_temp_new_i32();
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TCGv ttmp = tcg_const_tl(I16);
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tcg_gen_mul_tl(dst, cpu_R[ra], ttmp);
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tcg_gen_ext_i32_i64(t1, dst);
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tcg_gen_concat_i32_i64(t2, maclo, machi);
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tcg_gen_add_i64(t2, t2, t1);
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tcg_gen_extrl_i64_i32(maclo, t2);
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tcg_gen_shri_i64(t2, t2, 32);
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tcg_gen_extrl_i64_i32(machi, t2);
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tcg_temp_free_i32(dst);
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tcg_temp_free(ttmp);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t2);
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}
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t0 = tcg_const_tl(I16);
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gen_mac(dc, cpu_R[ra], t0);
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tcg_temp_free(t0);
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break;
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case 0x09: /* l.rfe */
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@ -873,40 +908,12 @@ static void dec_mac(DisasContext *dc, uint32_t insn)
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switch (op0) {
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case 0x0001: /* l.mac */
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LOG_DIS("l.mac r%d, r%d\n", ra, rb);
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
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tcg_gen_ext_i32_i64(t1, t0);
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tcg_gen_concat_i32_i64(t2, maclo, machi);
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tcg_gen_add_i64(t2, t2, t1);
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tcg_gen_extrl_i64_i32(maclo, t2);
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tcg_gen_shri_i64(t2, t2, 32);
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tcg_gen_extrl_i64_i32(machi, t2);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t2);
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}
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gen_mac(dc, cpu_R[ra], cpu_R[rb]);
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break;
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case 0x0002: /* l.msb */
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LOG_DIS("l.msb r%d, r%d\n", ra, rb);
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
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tcg_gen_ext_i32_i64(t1, t0);
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tcg_gen_concat_i32_i64(t2, maclo, machi);
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tcg_gen_sub_i64(t2, t2, t1);
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tcg_gen_extrl_i64_i32(maclo, t2);
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tcg_gen_shri_i64(t2, t2, 32);
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tcg_gen_extrl_i64_i32(machi, t2);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t2);
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}
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gen_msb(dc, cpu_R[ra], cpu_R[rb]);
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break;
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default:
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@ -969,9 +976,8 @@ static void dec_M(DisasContext *dc, uint32_t insn)
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case 0x1: /* l.macrc */
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LOG_DIS("l.macrc r%d\n", rd);
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tcg_gen_mov_tl(cpu_R[rd], maclo);
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tcg_gen_movi_tl(maclo, 0x0);
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tcg_gen_movi_tl(machi, 0x0);
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tcg_gen_trunc_i64_tl(cpu_R[rd], cpu_mac);
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tcg_gen_movi_i64(cpu_mac, 0);
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break;
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default:
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