target/mips: Convert CFCMSA opcode to decodetree
Convert the CFCMSA (Copy From Control MSA register) opcode to decodetree. Since it overlaps with the SPLATI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-29-f4bug@amsat.org>
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@ -168,7 +168,10 @@ BNZ 010001 111 .. ..... ................ @bz
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HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
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HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
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SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
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SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
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{
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CFCMSA 011110 0001111110 ..... ..... 011001 @elm
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SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
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SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
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}
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{
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{
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MOVE_V 011110 0010111110 ..... ..... 011001 @elm
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MOVE_V 011110 0010111110 ..... ..... 011001 @elm
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COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
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COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
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@ -45,7 +45,6 @@ enum {
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enum {
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enum {
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/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
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/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
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OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
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OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
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OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
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};
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};
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static const char msaregnames[][6] = {
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static const char msaregnames[][6] = {
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@ -551,7 +550,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
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uint8_t source = (ctx->opcode >> 11) & 0x1f;
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uint8_t source = (ctx->opcode >> 11) & 0x1f;
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uint8_t dest = (ctx->opcode >> 6) & 0x1f;
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uint8_t dest = (ctx->opcode >> 6) & 0x1f;
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TCGv telm = tcg_temp_new();
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TCGv telm = tcg_temp_new();
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TCGv_i32 tsr = tcg_const_i32(source);
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TCGv_i32 tdt = tcg_const_i32(dest);
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TCGv_i32 tdt = tcg_const_i32(dest);
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switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
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switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
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@ -559,10 +557,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
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gen_load_gpr(telm, source);
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gen_load_gpr(telm, source);
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gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
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gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
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break;
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break;
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case OPC_CFCMSA:
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gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
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gen_store_gpr(telm, dest);
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break;
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default:
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default:
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MIPS_INVAL("MSA instruction");
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MIPS_INVAL("MSA instruction");
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gen_reserved_instruction(ctx);
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gen_reserved_instruction(ctx);
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@ -571,7 +565,24 @@ static void gen_msa_elm_3e(DisasContext *ctx)
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tcg_temp_free(telm);
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tcg_temp_free(telm);
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tcg_temp_free_i32(tdt);
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tcg_temp_free_i32(tdt);
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tcg_temp_free_i32(tsr);
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}
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static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
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{
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TCGv telm;
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if (!check_msa_enabled(ctx)) {
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return true;
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}
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telm = tcg_temp_new();
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gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
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gen_store_gpr(telm, a->wd);
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tcg_temp_free(telm);
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return true;
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}
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}
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static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a,
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static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a,
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@ -663,7 +674,7 @@ static void gen_msa_elm(DisasContext *ctx)
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uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
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uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
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if (dfn == 0x3E) {
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if (dfn == 0x3E) {
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/* CTCMSA, CFCMSA */
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/* CTCMSA */
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gen_msa_elm_3e(ctx);
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gen_msa_elm_3e(ctx);
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return;
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return;
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} else {
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} else {
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