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target/mips: Convert CFCMSA opcode to decodetree 

Convert the CFCMSA (Copy From Control MSA register) opcode
to decodetree. Since it overlaps with the SPLATI opcode,
use a decodetree overlap group.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-29-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 18:29:14 +02:00
parent 62ba0e855a
commit 6f74237691
2 changed files with 23 additions and 9 deletions
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3
target/mips/tcg/msa.decode
View File

@ -168,7 +168,10 @@ BNZ 010001 111 .. ..... ................ @bz
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
{
CFCMSA 011110 0001111110 ..... ..... 011001 @elm
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
}
{ {
MOVE_V 011110 0010111110 ..... ..... 011001 @elm MOVE_V 011110 0010111110 ..... ..... 011001 @elm
COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df

27
target/mips/tcg/msa_translate.c
View File

@ -45,7 +45,6 @@ enum {
enum { enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
}; };
static const char msaregnames[][6] = { static const char msaregnames[][6] = {
@ -551,7 +550,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
uint8_t source = (ctx->opcode >> 11) & 0x1f; uint8_t source = (ctx->opcode >> 11) & 0x1f;
uint8_t dest = (ctx->opcode >> 6) & 0x1f; uint8_t dest = (ctx->opcode >> 6) & 0x1f;
TCGv telm = tcg_temp_new(); TCGv telm = tcg_temp_new();
TCGv_i32 tsr = tcg_const_i32(source);
TCGv_i32 tdt = tcg_const_i32(dest); TCGv_i32 tdt = tcg_const_i32(dest);
switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
@ -559,10 +557,6 @@ static void gen_msa_elm_3e(DisasContext *ctx)
gen_load_gpr(telm, source); gen_load_gpr(telm, source);
gen_helper_msa_ctcmsa(cpu_env, telm, tdt); gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
break; break;
case OPC_CFCMSA:
gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
gen_store_gpr(telm, dest);
break;
default: default:
MIPS_INVAL("MSA instruction"); MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
@ -571,7 +565,24 @@ static void gen_msa_elm_3e(DisasContext *ctx)
tcg_temp_free(telm); tcg_temp_free(telm);
tcg_temp_free_i32(tdt); tcg_temp_free_i32(tdt);
tcg_temp_free_i32(tsr); }
static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
{
TCGv telm;
if (!check_msa_enabled(ctx)) {
return true;
}
telm = tcg_temp_new();
gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
gen_store_gpr(telm, a->wd);
tcg_temp_free(telm);
return true;
} }
static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a,
@ -663,7 +674,7 @@ static void gen_msa_elm(DisasContext *ctx)
uint8_t dfn = (ctx->opcode >> 16) & 0x3f; uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
if (dfn == 0x3E) { if (dfn == 0x3E) {
/* CTCMSA, CFCMSA */ /* CTCMSA */
gen_msa_elm_3e(ctx); gen_msa_elm_3e(ctx);
return; return;
} else { } else {