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target/nios2: Replace MMU_LOG with tracepoints

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-02-25 21:06:20 -10:00
parent 1fb877a467
commit 6f83e277eb
3 changed files with 39 additions and 68 deletions
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1
meson.build
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@ -2705,6 +2705,7 @@ if have_system or have_user
'target/i386',
'target/i386/kvm',
'target/mips/tcg',
'target/nios2',
'target/ppc',
'target/riscv',
'target/s390x',

96
target/nios2/mmu.c
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@ -23,18 +23,10 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "mmu.h"
#include "trace/trace-target_nios2.h"
#if !defined(CONFIG_USER_ONLY)
/* Define this to enable MMU debug messages */
/* #define DEBUG_MMU */
#ifdef DEBUG_MMU
#define MMU_LOG(x) x
#else
#define MMU_LOG(x)
#endif
/* rw - 0 = read, 1 = write, 2 = fetch. */
unsigned int mmu_translate(CPUNios2State *env,
Nios2MMULookup *lu,
@ -43,37 +35,26 @@ unsigned int mmu_translate(CPUNios2State *env,
Nios2CPU *cpu = env_archcpu(env);
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
int vpn = vaddr >> 12;
int way, n_ways = cpu->tlb_num_ways;
MMU_LOG(qemu_log("mmu_translate vaddr %08X, pid %08X, vpn %08X\n",
vaddr, pid, vpn));
int way;
for (way = 0; way < cpu->tlb_num_ways; way++) {
Nios2TLBEntry *entry =
&env->mmu.tlb[(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask)];
MMU_LOG(qemu_log("TLB[%d] TAG %08X, VPN %08X\n",
(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask),
entry->tag, (entry->tag >> 12)));
for (way = 0; way < n_ways; way++) {
uint32_t index = (way * n_ways) + (vpn & env->mmu.tlb_entry_mask);
Nios2TLBEntry *entry = &env->mmu.tlb[index];
if (((entry->tag >> 12) != vpn) ||
(((entry->tag & (1 << 11)) == 0) &&
((entry->tag & ((1 << cpu->pid_num_bits) - 1)) != pid))) {
trace_nios2_mmu_translate_miss(vaddr, pid, index, entry->tag);
continue;
}
lu->vaddr = vaddr & TARGET_PAGE_MASK;
lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS;
lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) |
((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) |
((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0);
MMU_LOG(qemu_log("HIT TLB[%d] %08X %08X %08X\n",
(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask),
lu->vaddr, lu->paddr, lu->prot));
trace_nios2_mmu_translate_hit(vaddr, pid, index, lu->paddr, lu->prot);
return 1;
}
return 0;
@ -84,21 +65,18 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
CPUState *cs = env_cpu(env);
Nios2CPU *cpu = env_archcpu(env);
int idx;
MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));
for (idx = 0; idx < cpu->tlb_num_entries; idx++) {
Nios2TLBEntry *entry = &env->mmu.tlb[idx];
MMU_LOG(qemu_log("TLB[%d] => %08X %08X\n",
idx, entry->tag, entry->data));
if ((entry->tag & (1 << 10)) && (!(entry->tag & (1 << 11))) &&
((entry->tag & ((1 << cpu->pid_num_bits) - 1)) == pid)) {
uint32_t vaddr = entry->tag & TARGET_PAGE_MASK;
MMU_LOG(qemu_log("TLB Flush Page %08X\n", vaddr));
trace_nios2_mmu_flush_pid_hit(pid, idx, vaddr);
tlb_flush_page(cs, vaddr);
} else {
trace_nios2_mmu_flush_pid_miss(pid, idx, entry->tag);
}
}
}
@ -108,18 +86,15 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
CPUState *cs = env_cpu(env);
Nios2CPU *cpu = env_archcpu(env);
MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));
switch (rn) {
case CR_TLBACC:
MMU_LOG(qemu_log("TLBACC: IG %02X, FLAGS %c%c%c%c%c, PFN %05X\n",
v >> CR_TLBACC_IGN_SHIFT,
(v & CR_TLBACC_C) ? 'C' : '.',
(v & CR_TLBACC_R) ? 'R' : '.',
(v & CR_TLBACC_W) ? 'W' : '.',
(v & CR_TLBACC_X) ? 'X' : '.',
(v & CR_TLBACC_G) ? 'G' : '.',
v & CR_TLBACC_PFN_MASK));
trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT,
(v & CR_TLBACC_C) ? 'C' : '.',
(v & CR_TLBACC_R) ? 'R' : '.',
(v & CR_TLBACC_W) ? 'W' : '.',
(v & CR_TLBACC_X) ? 'X' : '.',
(v & CR_TLBACC_G) ? 'G' : '.',
v & CR_TLBACC_PFN_MASK);
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
@ -138,16 +113,10 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
if ((entry->tag != newTag) || (entry->data != newData)) {
if (entry->tag & (1 << 10)) {
/* Flush existing entry */
MMU_LOG(qemu_log("TLB Flush Page (OLD) %08X\n",
entry->tag & TARGET_PAGE_MASK));
tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK);
}
entry->tag = newTag;
entry->data = newData;
MMU_LOG(qemu_log("TLB[%d] = %08X %08X\n",
(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask),
entry->tag, entry->data));
}
/* Auto-increment tlbmisc.WAY */
env->regs[CR_TLBMISC] =
@ -161,15 +130,14 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
break;
case CR_TLBMISC:
MMU_LOG(qemu_log("TLBMISC: WAY %X, FLAGS %c%c%c%c%c%c, PID %04X\n",
v >> CR_TLBMISC_WAY_SHIFT,
(v & CR_TLBMISC_RD) ? 'R' : '.',
(v & CR_TLBMISC_WR) ? 'W' : '.',
(v & CR_TLBMISC_DBL) ? '2' : '.',
(v & CR_TLBMISC_BAD) ? 'B' : '.',
(v & CR_TLBMISC_PERM) ? 'P' : '.',
(v & CR_TLBMISC_D) ? 'D' : '.',
(v & CR_TLBMISC_PID_MASK) >> 4));
trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
(v & CR_TLBMISC_RD) ? 'R' : '.',
(v & CR_TLBMISC_WR) ? 'W' : '.',
(v & CR_TLBMISC_DBL) ? '2' : '.',
(v & CR_TLBMISC_BAD) ? 'B' : '.',
(v & CR_TLBMISC_PERM) ? 'P' : '.',
(v & CR_TLBMISC_D) ? 'D' : '.',
(v & CR_TLBMISC_PID_MASK) >> 4);
if ((v & CR_TLBMISC_PID_MASK) !=
(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
@ -193,11 +161,6 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
CR_TLBMISC_PID_SHIFT);
env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
MMU_LOG(qemu_log("TLB READ way %d, vpn %05X, tag %08X, data %08X, "
"tlbacc %08X, tlbmisc %08X, pteaddr %08X\n",
way, vpn, entry->tag, entry->data,
env->regs[CR_TLBACC], env->regs[CR_TLBMISC],
env->regs[CR_PTEADDR]));
} else {
env->regs[CR_TLBMISC] = v;
}
@ -206,9 +169,8 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
break;
case CR_PTEADDR:
MMU_LOG(qemu_log("PTEADDR: PTBASE %03X, VPN %05X\n",
v >> CR_PTEADDR_PTBASE_SHIFT,
(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT));
trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT,
(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT);
/* Writes to PTEADDR don't change the read-back VPN value */
env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
@ -226,8 +188,6 @@ void mmu_init(CPUNios2State *env)
Nios2CPU *cpu = env_archcpu(env);
Nios2MMU *mmu = &env->mmu;
MMU_LOG(qemu_log("mmu_init\n"));
mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1;
mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries);
}

10
target/nios2/trace-events Normal file
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@ -0,0 +1,10 @@
# mmu.c
nios2_mmu_translate_miss(uint32_t vaddr, uint32_t pid, uint32_t index, uint32_t tag) "mmu_translate: MISS vaddr=0x%08x pid=%u TLB[%u] tag=0x%08x"
nios2_mmu_translate_hit(uint32_t vaddr, uint32_t pid, uint32_t index, uint32_t paddr, uint32_t prot) "mmu_translate: HIT vaddr=0x%08x pid=%u TLB[%u] paddr=0x%08x prot=0x%x"
nios2_mmu_flush_pid_miss(uint32_t pid, uint32_t index, uint32_t vaddr) "mmu_flush: MISS pid=%u TLB[%u] tag=0x%08x"
nios2_mmu_flush_pid_hit(uint32_t pid, uint32_t index, uint32_t vaddr) "mmu_flush: HIT pid=%u TLB[%u] vaddr=0x%08x"
nios2_mmu_write_tlbacc(uint32_t ig, char c, char r, char w, char x, char g, uint32_t pfn) "mmu_write_tlbacc: ig=0x%02x flags=%c%c%c%c%c pfn=0x%08x"
nios2_mmu_write_tlbmisc(uint32_t way, char r, char w, char t, char b, char p, char d, uint32_t pid) "mmu_write_tlbmisc: way=0x%x flags=%c%c%c%c%c%c pid=%u"
nios2_mmu_write_pteaddr(uint32_t ptb, uint32_t vpn) "mmu_write_pteaddr: ptbase=0x%03x vpn=0x%05x"