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hw/isa/piix3: Create USB controller in host device

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The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.

Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-13-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bernhard Beschow 2023-10-07 14:38:20 +02:00 committed by Michael S. Tsirkin
parent e47e5a5b79
commit 6fe4464c05
4 changed files with 23 additions and 5 deletions
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7
hw/i386/pc_piix.c
View File

@ -51,7 +51,6 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@ -265,6 +264,8 @@ static void pc_init1(MachineState *machine,
size_t i;
pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
object_property_set_bool(OBJECT(pci_dev), "has-usb",
machine_usb(machine), &error_abort);
dev = DEVICE(pci_dev);
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
@ -359,10 +360,6 @@ static void pc_init1(MachineState *machine,
}
#endif
if (pcmc->pci_enabled && machine_usb(machine)) {
pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
}
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;

1
hw/isa/Kconfig
View File

@ -37,6 +37,7 @@ config PIIX3
select IDE_PIIX
select ISA_BUS
select MC146818RTC
select USB_UHCI
config PIIX4
bool

16
hw/isa/piix3.c
View File

@ -298,6 +298,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
return;
}
/* USB */
if (d->has_usb) {
object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
TYPE_PIIX3_USB_UHCI);
qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
return;
}
}
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@ -332,6 +342,11 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
static Property pci_piix3_props[] = {
DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
DEFINE_PROP_END_OF_LIST(),
};
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -352,6 +367,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}

4
include/hw/southbridge/piix.h
View File

@ -15,6 +15,7 @@
#include "hw/pci/pci_device.h"
#include "hw/ide/pci.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@ -54,12 +55,15 @@ struct PIIXState {
MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci;
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
bool has_usb;
};
typedef struct PIIXState PIIX3State;