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target-mips: fix EntryHi.EHINV being cleared on TLB exception

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While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Leon Alrae 2016-07-28 09:28:23 +01:00
parent 7f81dbb9a0
commit 701074a6fc
1 changed files with 1 additions and 0 deletions
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1
target-mips/helper.c
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@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
env->CP0_Context = (env->CP0_Context & ~0x007fffff) | env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
((address >> 9) & 0x007ffff0); ((address >> 9) & 0x007ffff0);
env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
(env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
(address & (TARGET_PAGE_MASK << 1)); (address & (TARGET_PAGE_MASK << 1));
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
env->CP0_EntryHi &= env->SEGMask; env->CP0_EntryHi &= env->SEGMask;