target/ppc: Avoid tcg_const_* in translate.c
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
9d15d8e1bb
commit
7058ff5231
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@ -263,8 +263,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
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* faulting instruction
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*/
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gen_update_nip(ctx, ctx->cia);
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t0 = tcg_const_i32(excp);
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t1 = tcg_const_i32(error);
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t0 = tcg_constant_i32(excp);
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t1 = tcg_constant_i32(error);
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gen_helper_raise_exception_err(cpu_env, t0, t1);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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@ -278,7 +278,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
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* faulting instruction
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*/
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gen_update_nip(ctx, ctx->cia);
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t0 = tcg_const_i32(excp);
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t0 = tcg_constant_i32(excp);
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gen_helper_raise_exception(cpu_env, t0);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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@ -289,7 +289,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
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TCGv_i32 t0;
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gen_update_nip(ctx, nip);
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t0 = tcg_const_i32(excp);
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t0 = tcg_constant_i32(excp);
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gen_helper_raise_exception(cpu_env, t0);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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@ -386,7 +386,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
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static void spr_load_dump_spr(int sprn)
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{
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#ifdef PPC_DUMP_SPR_ACCESSES
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TCGv_i32 t0 = tcg_const_i32(sprn);
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TCGv_i32 t0 = tcg_constant_i32(sprn);
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gen_helper_load_dump_spr(cpu_env, t0);
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#endif
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}
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@ -400,7 +400,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
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static void spr_store_dump_spr(int sprn)
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{
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#ifdef PPC_DUMP_SPR_ACCESSES
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TCGv_i32 t0 = tcg_const_i32(sprn);
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TCGv_i32 t0 = tcg_constant_i32(sprn);
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gen_helper_store_dump_spr(cpu_env, t0);
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#endif
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}
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@ -672,25 +672,25 @@ void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
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void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
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TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
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gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
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}
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void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
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TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
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gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
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}
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void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
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TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
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gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
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}
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void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
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TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
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gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
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}
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@ -712,25 +712,25 @@ void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
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void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
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TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
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gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
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}
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void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
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TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
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gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
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}
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void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
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TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
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gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
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}
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void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
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TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
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gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
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}
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@ -1040,13 +1040,15 @@ void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
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void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv_i32 t0 = tcg_const_i32(sprn);
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TCGv_i32 t0 = tcg_constant_i32(sprn);
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gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
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}
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void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
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{
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gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
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}
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void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
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{
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gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
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@ -1080,9 +1082,9 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
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static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
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int bit, int sprn, int cause)
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{
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TCGv_i32 t1 = tcg_const_i32(bit);
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TCGv_i32 t2 = tcg_const_i32(sprn);
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TCGv_i32 t3 = tcg_const_i32(cause);
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TCGv_i32 t1 = tcg_constant_i32(bit);
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TCGv_i32 t2 = tcg_constant_i32(sprn);
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TCGv_i32 t3 = tcg_constant_i32(cause);
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gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
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}
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@ -1090,9 +1092,9 @@ static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
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static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
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int bit, int sprn, int cause)
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{
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TCGv_i32 t1 = tcg_const_i32(bit);
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TCGv_i32 t2 = tcg_const_i32(sprn);
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TCGv_i32 t3 = tcg_const_i32(cause);
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TCGv_i32 t1 = tcg_constant_i32(bit);
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TCGv_i32 t2 = tcg_constant_i32(sprn);
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TCGv_i32 t3 = tcg_constant_i32(cause);
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gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
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}
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@ -1388,7 +1390,7 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
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static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
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{
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TCGv t0 = tcg_const_tl(arg1);
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TCGv t0 = tcg_constant_tl(arg1);
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gen_op_cmp(arg0, t0, s, crf);
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}
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@ -1409,7 +1411,7 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
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static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
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{
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TCGv t0 = tcg_const_tl(arg1);
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TCGv t0 = tcg_constant_tl(arg1);
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gen_op_cmp32(arg0, t0, s, crf);
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}
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@ -1476,7 +1478,7 @@ static void gen_isel(DisasContext *ctx)
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tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
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tcg_gen_andi_tl(t0, t0, mask);
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zr = tcg_const_tl(0);
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zr = tcg_constant_tl(0);
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tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
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rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
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cpu_gpr[rB(ctx->opcode)]);
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@ -1568,7 +1570,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
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tcg_gen_mov_tl(ca32, ca);
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}
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} else {
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TCGv zero = tcg_const_tl(0);
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TCGv zero = tcg_constant_tl(0);
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if (add_ca) {
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tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
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tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
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@ -1609,7 +1611,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
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add_ca, compute_ca, compute_ov) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv t0 = tcg_const_tl(const_val); \
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TCGv t0 = tcg_constant_tl(const_val); \
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gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
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cpu_gpr[rA(ctx->opcode)], t0, \
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ca, glue(ca, 32), \
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@ -1636,7 +1638,7 @@ GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
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/* addic addic.*/
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static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
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{
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TCGv c = tcg_const_tl(SIMM(ctx->opcode));
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TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
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gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
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}
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@ -1709,7 +1711,7 @@ GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
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#define GEN_DIVE(name, hlpr, compute_ov) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i32 t0 = tcg_const_i32(compute_ov); \
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TCGv_i32 t0 = tcg_constant_i32(compute_ov); \
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gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
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cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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@ -1802,8 +1804,8 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
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tcg_gen_rem_i32(t3, t0, t1);
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tcg_gen_ext_i32_tl(ret, t3);
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} else {
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TCGv_i32 t2 = tcg_const_i32(1);
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TCGv_i32 t3 = tcg_const_i32(0);
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TCGv_i32 t2 = tcg_constant_i32(1);
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TCGv_i32 t3 = tcg_constant_i32(0);
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tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
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tcg_gen_remu_i32(t3, t0, t1);
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tcg_gen_extu_i32_tl(ret, t3);
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@ -1842,8 +1844,8 @@ static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
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tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
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tcg_gen_rem_i64(ret, t0, t1);
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} else {
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TCGv_i64 t2 = tcg_const_i64(1);
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TCGv_i64 t3 = tcg_const_i64(0);
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TCGv_i64 t2 = tcg_constant_i64(1);
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TCGv_i64 t3 = tcg_constant_i64(0);
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tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
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tcg_gen_remu_i64(ret, t0, t1);
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}
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@ -2038,7 +2040,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
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} else if (add_ca) {
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TCGv zero, inv1 = tcg_temp_new();
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tcg_gen_not_tl(inv1, arg1);
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zero = tcg_const_tl(0);
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zero = tcg_constant_tl(0);
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tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
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tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
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gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
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@ -2083,7 +2085,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
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add_ca, compute_ca, compute_ov) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv t0 = tcg_const_tl(const_val); \
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TCGv t0 = tcg_constant_tl(const_val); \
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gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
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cpu_gpr[rA(ctx->opcode)], t0, \
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add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
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@ -2107,7 +2109,7 @@ GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
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/* subfic */
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static void gen_subfic(DisasContext *ctx)
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{
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TCGv c = tcg_const_tl(SIMM(ctx->opcode));
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TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
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gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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c, 0, 1, 0, 0);
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}
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@ -2115,7 +2117,7 @@ static void gen_subfic(DisasContext *ctx)
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/* neg neg. nego nego. */
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static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
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{
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TCGv zero = tcg_const_tl(0);
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TCGv zero = tcg_constant_tl(0);
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gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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zero, 0, 0, compute_ov, Rc(ctx->opcode));
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}
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@ -2214,7 +2216,7 @@ GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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static void gen_pause(DisasContext *ctx)
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{
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TCGv_i32 t0 = tcg_const_i32(0);
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TCGv_i32 t0 = tcg_constant_i32(0);
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tcg_gen_st_i32(t0, cpu_env,
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-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
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@ -3256,7 +3258,7 @@ static void gen_lmw(DisasContext *ctx)
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}
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gen_set_access_type(ctx, ACCESS_INT);
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t0 = tcg_temp_new();
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t1 = tcg_const_i32(rD(ctx->opcode));
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t1 = tcg_constant_i32(rD(ctx->opcode));
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gen_addr_imm_index(ctx, t0, 0);
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gen_helper_lmw(cpu_env, t0, t1);
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}
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@ -3273,7 +3275,7 @@ static void gen_stmw(DisasContext *ctx)
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}
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gen_set_access_type(ctx, ACCESS_INT);
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t0 = tcg_temp_new();
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t1 = tcg_const_i32(rS(ctx->opcode));
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t1 = tcg_constant_i32(rS(ctx->opcode));
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gen_addr_imm_index(ctx, t0, 0);
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gen_helper_stmw(cpu_env, t0, t1);
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}
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@ -3311,8 +3313,8 @@ static void gen_lswi(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_INT);
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t0 = tcg_temp_new();
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gen_addr_register(ctx, t0);
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t1 = tcg_const_i32(nb);
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t2 = tcg_const_i32(start);
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t1 = tcg_constant_i32(nb);
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t2 = tcg_constant_i32(start);
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gen_helper_lsw(cpu_env, t0, t1, t2);
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}
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@ -3329,9 +3331,9 @@ static void gen_lswx(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_INT);
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t0 = tcg_temp_new();
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gen_addr_reg_index(ctx, t0);
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t1 = tcg_const_i32(rD(ctx->opcode));
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t2 = tcg_const_i32(rA(ctx->opcode));
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t3 = tcg_const_i32(rB(ctx->opcode));
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t1 = tcg_constant_i32(rD(ctx->opcode));
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t2 = tcg_constant_i32(rA(ctx->opcode));
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||||
t3 = tcg_constant_i32(rB(ctx->opcode));
|
||||
gen_helper_lswx(cpu_env, t0, t1, t2, t3);
|
||||
}
|
||||
|
||||
|
|
@ -3352,8 +3354,8 @@ static void gen_stswi(DisasContext *ctx)
|
|||
if (nb == 0) {
|
||||
nb = 32;
|
||||
}
|
||||
t1 = tcg_const_i32(nb);
|
||||
t2 = tcg_const_i32(rS(ctx->opcode));
|
||||
t1 = tcg_constant_i32(nb);
|
||||
t2 = tcg_constant_i32(rS(ctx->opcode));
|
||||
gen_helper_stsw(cpu_env, t0, t1, t2);
|
||||
}
|
||||
|
||||
|
|
@ -3373,7 +3375,7 @@ static void gen_stswx(DisasContext *ctx)
|
|||
t1 = tcg_temp_new_i32();
|
||||
tcg_gen_trunc_tl_i32(t1, cpu_xer);
|
||||
tcg_gen_andi_i32(t1, t1, 0x7F);
|
||||
t2 = tcg_const_i32(rS(ctx->opcode));
|
||||
t2 = tcg_constant_i32(rS(ctx->opcode));
|
||||
gen_helper_stsw(cpu_env, t0, t1, t2);
|
||||
}
|
||||
|
||||
|
|
@ -3943,7 +3945,7 @@ static void gen_wait(DisasContext *ctx)
|
|||
* to occur.
|
||||
*/
|
||||
if (wc == 0) {
|
||||
TCGv_i32 t0 = tcg_const_i32(1);
|
||||
TCGv_i32 t0 = tcg_constant_i32(1);
|
||||
tcg_gen_st_i32(t0, cpu_env,
|
||||
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
|
||||
/* Stop translation, as the CPU is supposed to sleep from now */
|
||||
|
|
@ -3989,7 +3991,7 @@ static void gen_doze(DisasContext *ctx)
|
|||
TCGv_i32 t;
|
||||
|
||||
CHK_HV(ctx);
|
||||
t = tcg_const_i32(PPC_PM_DOZE);
|
||||
t = tcg_constant_i32(PPC_PM_DOZE);
|
||||
gen_helper_pminsn(cpu_env, t);
|
||||
/* Stop translation, as the CPU is supposed to sleep from now */
|
||||
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
|
||||
|
|
@ -4004,7 +4006,7 @@ static void gen_nap(DisasContext *ctx)
|
|||
TCGv_i32 t;
|
||||
|
||||
CHK_HV(ctx);
|
||||
t = tcg_const_i32(PPC_PM_NAP);
|
||||
t = tcg_constant_i32(PPC_PM_NAP);
|
||||
gen_helper_pminsn(cpu_env, t);
|
||||
/* Stop translation, as the CPU is supposed to sleep from now */
|
||||
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
|
||||
|
|
@ -4019,7 +4021,7 @@ static void gen_stop(DisasContext *ctx)
|
|||
TCGv_i32 t;
|
||||
|
||||
CHK_HV(ctx);
|
||||
t = tcg_const_i32(PPC_PM_STOP);
|
||||
t = tcg_constant_i32(PPC_PM_STOP);
|
||||
gen_helper_pminsn(cpu_env, t);
|
||||
/* Stop translation, as the CPU is supposed to sleep from now */
|
||||
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
|
||||
|
|
@ -4034,7 +4036,7 @@ static void gen_sleep(DisasContext *ctx)
|
|||
TCGv_i32 t;
|
||||
|
||||
CHK_HV(ctx);
|
||||
t = tcg_const_i32(PPC_PM_SLEEP);
|
||||
t = tcg_constant_i32(PPC_PM_SLEEP);
|
||||
gen_helper_pminsn(cpu_env, t);
|
||||
/* Stop translation, as the CPU is supposed to sleep from now */
|
||||
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
|
||||
|
|
@ -4049,7 +4051,7 @@ static void gen_rvwinkle(DisasContext *ctx)
|
|||
TCGv_i32 t;
|
||||
|
||||
CHK_HV(ctx);
|
||||
t = tcg_const_i32(PPC_PM_RVWINKLE);
|
||||
t = tcg_constant_i32(PPC_PM_RVWINKLE);
|
||||
gen_helper_pminsn(cpu_env, t);
|
||||
/* Stop translation, as the CPU is supposed to sleep from now */
|
||||
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
|
||||
|
|
@ -4506,7 +4508,7 @@ static void gen_tw(DisasContext *ctx)
|
|||
if (check_unconditional_trap(ctx)) {
|
||||
return;
|
||||
}
|
||||
t0 = tcg_const_i32(TO(ctx->opcode));
|
||||
t0 = tcg_constant_i32(TO(ctx->opcode));
|
||||
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
|
||||
t0);
|
||||
}
|
||||
|
|
@ -4520,8 +4522,8 @@ static void gen_twi(DisasContext *ctx)
|
|||
if (check_unconditional_trap(ctx)) {
|
||||
return;
|
||||
}
|
||||
t0 = tcg_const_tl(SIMM(ctx->opcode));
|
||||
t1 = tcg_const_i32(TO(ctx->opcode));
|
||||
t0 = tcg_constant_tl(SIMM(ctx->opcode));
|
||||
t1 = tcg_constant_i32(TO(ctx->opcode));
|
||||
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
|
||||
}
|
||||
|
||||
|
|
@ -4534,7 +4536,7 @@ static void gen_td(DisasContext *ctx)
|
|||
if (check_unconditional_trap(ctx)) {
|
||||
return;
|
||||
}
|
||||
t0 = tcg_const_i32(TO(ctx->opcode));
|
||||
t0 = tcg_constant_i32(TO(ctx->opcode));
|
||||
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
|
||||
t0);
|
||||
}
|
||||
|
|
@ -4548,8 +4550,8 @@ static void gen_tdi(DisasContext *ctx)
|
|||
if (check_unconditional_trap(ctx)) {
|
||||
return;
|
||||
}
|
||||
t0 = tcg_const_tl(SIMM(ctx->opcode));
|
||||
t1 = tcg_const_i32(TO(ctx->opcode));
|
||||
t0 = tcg_constant_tl(SIMM(ctx->opcode));
|
||||
t1 = tcg_constant_i32(TO(ctx->opcode));
|
||||
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -5026,7 +5028,7 @@ static void gen_dcbz(DisasContext *ctx)
|
|||
|
||||
gen_set_access_type(ctx, ACCESS_CACHE);
|
||||
tcgv_addr = tcg_temp_new();
|
||||
tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
|
||||
tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
|
||||
gen_addr_reg_index(ctx, tcgv_addr);
|
||||
gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
|
||||
}
|
||||
|
|
@ -5039,7 +5041,7 @@ static void gen_dcbzep(DisasContext *ctx)
|
|||
|
||||
gen_set_access_type(ctx, ACCESS_CACHE);
|
||||
tcgv_addr = tcg_temp_new();
|
||||
tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
|
||||
tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
|
||||
gen_addr_reg_index(ctx, tcgv_addr);
|
||||
gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
|
||||
}
|
||||
|
|
@ -5114,7 +5116,7 @@ static void gen_mfsr(DisasContext *ctx)
|
|||
TCGv t0;
|
||||
|
||||
CHK_SV(ctx);
|
||||
t0 = tcg_const_tl(SR(ctx->opcode));
|
||||
t0 = tcg_constant_tl(SR(ctx->opcode));
|
||||
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
}
|
||||
|
|
@ -5143,7 +5145,7 @@ static void gen_mtsr(DisasContext *ctx)
|
|||
TCGv t0;
|
||||
|
||||
CHK_SV(ctx);
|
||||
t0 = tcg_const_tl(SR(ctx->opcode));
|
||||
t0 = tcg_constant_tl(SR(ctx->opcode));
|
||||
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
}
|
||||
|
|
@ -5175,7 +5177,7 @@ static void gen_mfsr_64b(DisasContext *ctx)
|
|||
TCGv t0;
|
||||
|
||||
CHK_SV(ctx);
|
||||
t0 = tcg_const_tl(SR(ctx->opcode));
|
||||
t0 = tcg_constant_tl(SR(ctx->opcode));
|
||||
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
}
|
||||
|
|
@ -5204,7 +5206,7 @@ static void gen_mtsr_64b(DisasContext *ctx)
|
|||
TCGv t0;
|
||||
|
||||
CHK_SV(ctx);
|
||||
t0 = tcg_const_tl(SR(ctx->opcode));
|
||||
t0 = tcg_constant_tl(SR(ctx->opcode));
|
||||
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
}
|
||||
|
|
@ -5558,7 +5560,7 @@ static void gen_mfdcr(DisasContext *ctx)
|
|||
TCGv dcrn;
|
||||
|
||||
CHK_SV(ctx);
|
||||
dcrn = tcg_const_tl(SPR(ctx->opcode));
|
||||
dcrn = tcg_constant_tl(SPR(ctx->opcode));
|
||||
gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
}
|
||||
|
|
@ -5572,7 +5574,7 @@ static void gen_mtdcr(DisasContext *ctx)
|
|||
TCGv dcrn;
|
||||
|
||||
CHK_SV(ctx);
|
||||
dcrn = tcg_const_tl(SPR(ctx->opcode));
|
||||
dcrn = tcg_constant_tl(SPR(ctx->opcode));
|
||||
gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
|
||||
}
|
||||
|
|
@ -5793,7 +5795,7 @@ static void gen_tlbre_440(DisasContext *ctx)
|
|||
case 1:
|
||||
case 2:
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
|
||||
TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
|
||||
gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
|
||||
t0, cpu_gpr[rA(ctx->opcode)]);
|
||||
}
|
||||
|
|
@ -5839,7 +5841,7 @@ static void gen_tlbwe_440(DisasContext *ctx)
|
|||
case 1:
|
||||
case 2:
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
|
||||
TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
|
||||
gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
|
||||
cpu_gpr[rS(ctx->opcode)]);
|
||||
}
|
||||
|
|
@ -5981,7 +5983,7 @@ static void gen_wrteei(DisasContext *ctx)
|
|||
/* dlmzb */
|
||||
static void gen_dlmzb(DisasContext *ctx)
|
||||
{
|
||||
TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
|
||||
TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
|
||||
gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
|
||||
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue