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Merge remote-tracking branch 'stefanha/trivial-patches' into staging 

Conflicts:
	cpu-all.h
This commit is contained in:
Anthony Liguori 2011-05-12 08:08:12 -05:00
parent 89bb563f69 2f172849b6
commit 711c21280b
55 changed files with 110 additions and 116 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Changelog
View File

@ -525,7 +525,7 @@ version 0.1.5:
- ppc64 support + personality() patch (Rusty Russell)
- first Alpha CPU patches (Falk Hueffner)
- removed bfd.h dependancy
- removed bfd.h dependency
- fixed shrd, shld, idivl and divl on PowerPC.
- fixed buggy glibc PowerPC rint() function (test-i386 passes now on PowerPC).

2
Makefile
View File

@ -88,6 +88,8 @@ include $(SRC_PATH)/Makefile.objs
endif
$(common-obj-y): $(GENERATED_HEADERS)
subdir-libcacard: $(oslib-obj-y) $(trace-obj-y) qemu-malloc.o qemu-timer-common.o
$(filter %-softmmu,$(SUBDIR_RULES)): $(trace-obj-y) $(common-obj-y) subdir-libdis
$(filter %-user,$(SUBDIR_RULES)): $(GENERATED_HEADERS) $(trace-obj-y) subdir-libdis-user subdir-libuser

9
Makefile.objs
View File

@ -7,8 +7,8 @@ qobject-obj-y += qerror.o
#######################################################################
# oslib-obj-y is code depending on the OS (win32 vs posix)
oslib-obj-y = osdep.o
oslib-obj-$(CONFIG_WIN32) += oslib-win32.o
oslib-obj-$(CONFIG_POSIX) += oslib-posix.o
oslib-obj-$(CONFIG_WIN32) += oslib-win32.o qemu-thread-win32.o
oslib-obj-$(CONFIG_POSIX) += oslib-posix.o qemu-thread-posix.o
#######################################################################
# block-obj-y is code used by both qemu system emulation and qemu-img
@ -143,8 +143,7 @@ common-obj-y += $(addprefix ui/, $(ui-obj-y))
common-obj-$(CONFIG_VNC) += $(addprefix ui/, $(vnc-obj-y))
common-obj-y += iov.o acl.o
common-obj-$(CONFIG_POSIX) += qemu-thread-posix.o compatfd.o
common-obj-$(CONFIG_WIN32) += qemu-thread-win32.o
common-obj-$(CONFIG_POSIX) += compatfd.o
common-obj-y += notify.o event_notifier.o
common-obj-y += qemu-timer.o qemu-timer-common.o
@ -335,7 +334,7 @@ trace-dtrace.h: trace-dtrace.dtrace
$(call quiet-command,dtrace -o $@ -h -s $<, " GEN trace-dtrace.h")
# Normal practice is to name DTrace probe file with a '.d' extension
# but that gets picked up by QEMU's Makefile as an external dependancy
# but that gets picked up by QEMU's Makefile as an external dependency
# rule file. So we use '.dtrace' instead
trace-dtrace.dtrace: trace-dtrace.dtrace-timestamp
trace-dtrace.dtrace-timestamp: $(SRC_PATH)/trace-events config-host.mak

4
block.c
View File

@ -455,7 +455,7 @@ static int bdrv_open_common(BlockDriverState *bs, const char *filename,
open_flags = flags & ~(BDRV_O_SNAPSHOT | BDRV_O_NO_BACKING);
/*
* Snapshots should be writeable.
* Snapshots should be writable.
*/
if (bs->is_temporary) {
open_flags |= BDRV_O_RDWR;
@ -747,7 +747,7 @@ DeviceState *bdrv_get_attached(BlockDriverState *bs)
* Run consistency checks on an image
*
* Returns 0 if the check could be completed (it doesn't mean that the image is
* free of errors) or -errno when an internal error occured. The results of the
* free of errors) or -errno when an internal error occurred. The results of the
* check are stored in res.
*/
int bdrv_check(BlockDriverState *bs, BdrvCheckResult *res)

2
block/qcow2-refcount.c
View File

@ -1063,7 +1063,7 @@ fail:
* Checks an image for refcount consistency.
*
* Returns 0 if no errors are found, the number of errors in case the image is
* detected as corrupted, and -errno when an internal error occured.
* detected as corrupted, and -errno when an internal error occurred.
*/
int qcow2_check_refcounts(BlockDriverState *bs, BdrvCheckResult *res)
{

4
block/sheepdog.c
View File

@ -196,7 +196,7 @@ static inline uint64_t fnv_64a_buf(void *buf, size_t len, uint64_t hval)
return hval;
}
static inline int is_data_obj_writeable(SheepdogInode *inode, unsigned int idx)
static inline int is_data_obj_writable(SheepdogInode *inode, unsigned int idx)
{
return inode->vdi_id == inode->data_vdi_id[idx];
}
@ -1577,7 +1577,7 @@ static void sd_readv_writev_bh_cb(void *p)
create = 1;
} else if (acb->aiocb_type == AIOCB_WRITE_UDATA
&& !is_data_obj_writeable(inode, idx)) {
&& !is_data_obj_writable(inode, idx)) {
/* Copy-On-Write */
create = 1;
old_oid = oid;

2
bsd-user/main.c
View File

@ -237,7 +237,7 @@ void cpu_loop(CPUX86State *env)
break;
#ifndef TARGET_ABI32
case EXCP_SYSCALL:
/* syscall from syscall intruction */
/* syscall from syscall instruction */
if (bsd_type == target_freebsd)
env->regs[R_EAX] = do_freebsd_syscall(env,
env->regs[R_EAX],

2
bsd-user/qemu.h
View File

@ -323,7 +323,7 @@ abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len);
abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len);
/* Functions for accessing guest memory. The tget and tput functions
read/write single values, byteswapping as neccessary. The lock_user
read/write single values, byteswapping as necessary. The lock_user
gets a pointer to a contiguous area of guest memory, but does not perform
and byteswapping. lock_user may return either a pointer to the guest
memory, or a temporary buffer. */

4
cpu-exec.c
View File

@ -503,7 +503,7 @@ int cpu_exec(CPUState *env1)
jump normally, then does the exception return when the
CPU tries to execute code at the magic address.
This will cause the magic PC value to be pushed to
the stack if an interrupt occured at the wrong time.
the stack if an interrupt occurred at the wrong time.
We avoid this by disabling interrupts when
pc contains a magic address. */
if (interrupt_request & CPU_INTERRUPT_HARD
@ -563,7 +563,7 @@ int cpu_exec(CPUState *env1)
next_tb = 0;
}
#endif
/* Don't use the cached interupt_request value,
/* Don't use the cached interrupt_request value,
do_interrupt may have updated the EXITTB flag. */
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;

2
darwin-user/syscall.c
View File

@ -977,7 +977,7 @@ long do_unix_syscall_indirect(void *cpu_env, int num)
#elif TARGET_PPC
{
int i;
/* XXX: not really needed those regs are volatile accross calls */
/* XXX: not really needed those regs are volatile across calls */
uint32_t **regs = ((CPUPPCState*)cpu_env)->gpr;
for(i = 11; i > 3; i--)
*regs[i] = *regs[i-1];

2
hppa-dis.c
View File

@ -1645,7 +1645,7 @@ static const char *const fp_reg_names[] =
typedef unsigned int CORE_ADDR;
/* Get at various relevent fields of an instruction word. */
/* Get at various relevant fields of an instruction word. */
#define MASK_5 0x1f
#define MASK_10 0x3ff

6
hw/ac97.c
View File

@ -1001,8 +1001,6 @@ static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
static void write_bup (AC97LinkState *s, int elapsed)
{
int written = 0;
dolog ("write_bup\n");
if (!(s->bup_flag & BUP_SET)) {
if (s->bup_flag & BUP_LAST) {
@ -1026,7 +1024,6 @@ static void write_bup (AC97LinkState *s, int elapsed)
return;
temp -= copied;
elapsed -= copied;
written += copied;
}
}
}
@ -1069,7 +1066,7 @@ static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
static void transfer_audio (AC97LinkState *s, int index, int elapsed)
{
AC97BusMasterRegs *r = &s->bm_regs[index];
int written = 0, stop = 0;
int stop = 0;
if (s->invalid_freq[index]) {
AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
@ -1114,7 +1111,6 @@ static void transfer_audio (AC97LinkState *s, int index, int elapsed)
switch (index) {
case PO_INDEX:
temp = write_audio (s, r, elapsed, &stop);
written += temp;
elapsed -= temp;
r->picb -= (temp >> 1);
break;

2
hw/bt.h
View File

@ -1441,7 +1441,7 @@ typedef struct {
#define EVT_FLUSH_OCCURRED 0x11
typedef struct {
uint16_t handle;
} __attribute__ ((packed)) evt_flush_occured;
} __attribute__ ((packed)) evt_flush_occurred;
#define EVT_FLUSH_OCCURRED_SIZE 2
#define EVT_ROLE_CHANGE 0x12

2
hw/eepro100.c
View File

@ -1126,7 +1126,7 @@ static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
{
TRACE(EEPROM, logout("val=0x%02x\n", val));
/* mask unwriteable bits */
/* mask unwritable bits */
#if 0
val = SET_MASKED(val, 0x31, eeprom->value);
#endif

10
hw/eeprom93xx.c
View File

@ -75,7 +75,7 @@ struct _eeprom_t {
uint8_t tick;
uint8_t address;
uint8_t command;
uint8_t writeable;
uint8_t writable;
uint8_t eecs;
uint8_t eesk;
@ -130,7 +130,7 @@ static const VMStateDescription vmstate_eeprom = {
VMSTATE_UINT8(tick, eeprom_t),
VMSTATE_UINT8(address, eeprom_t),
VMSTATE_UINT8(command, eeprom_t),
VMSTATE_UINT8(writeable, eeprom_t),
VMSTATE_UINT8(writable, eeprom_t),
VMSTATE_UINT8(eecs, eeprom_t),
VMSTATE_UINT8(eesk, eeprom_t),
@ -165,7 +165,7 @@ void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
address = 0x0;
} else if (eeprom->eecs && ! eecs) {
/* End chip select cycle. This triggers write / erase. */
if (eeprom->writeable) {
if (eeprom->writable) {
uint8_t subcommand = address >> (eeprom->addrbits - 2);
if (command == 0 && subcommand == 2) {
/* Erase all. */
@ -232,7 +232,7 @@ void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
switch (address >> (eeprom->addrbits - 2)) {
case 0:
logout("write disable command\n");
eeprom->writeable = 0;
eeprom->writable = 0;
break;
case 1:
logout("write all command\n");
@ -242,7 +242,7 @@ void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
break;
case 3:
logout("write enable command\n");
eeprom->writeable = 1;
eeprom->writable = 1;
break;
}
} else {

2
hw/lan9118.c
View File

@ -721,7 +721,7 @@ static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
break;
}
s->phy_control = val & 0x7980;
/* Complete autonegotiation imediately. */
/* Complete autonegotiation immediately. */
if (val & 0x1000) {
s->phy_status |= 0x0020;
}

18
hw/lsi53c895a.c
View File

@ -189,7 +189,7 @@ typedef struct {
uint32_t script_ram_base;
int carry; /* ??? Should this be an a visible register somewhere? */
int sense;
int status;
/* Action to take at the end of a MSG IN phase.
0 = COMMAND, 1 = disconnect, 2 = DATA OUT, 3 = DATA IN. */
int msg_action;
@ -695,8 +695,8 @@ static void lsi_command_complete(SCSIBus *bus, int reason, uint32_t tag,
out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
if (reason == SCSI_REASON_DONE) {
DPRINTF("Command complete sense=%d\n", (int)arg);
s->sense = arg;
DPRINTF("Command complete status=%d\n", (int)arg);
s->status = arg;
s->command_complete = 2;
if (s->waiting && s->dbc != 0) {
/* Raise phase mismatch for short transfers. */
@ -783,14 +783,14 @@ static void lsi_do_command(LSIState *s)
static void lsi_do_status(LSIState *s)
{
uint8_t sense;
DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
uint8_t status;
DPRINTF("Get status len=%d status=%d\n", s->dbc, s->status);
if (s->dbc != 1)
BADF("Bad Status move\n");
s->dbc = 1;
sense = s->sense;
s->sfbr = sense;
cpu_physical_memory_write(s->dnad, &sense, 1);
status = s->status;
s->sfbr = status;
cpu_physical_memory_write(s->dnad, &status, 1);
lsi_set_phase(s, PHASE_MI);
s->msg_action = 1;
lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
@ -2122,7 +2122,7 @@ static const VMStateDescription vmstate_lsi_scsi = {
VMSTATE_PCI_DEVICE(dev, LSIState),
VMSTATE_INT32(carry, LSIState),
VMSTATE_INT32(sense, LSIState),
VMSTATE_INT32(status, LSIState),
VMSTATE_INT32(msg_action, LSIState),
VMSTATE_INT32(msg_len, LSIState),
VMSTATE_BUFFER(msg, LSIState),

2
hw/msi.c
View File

@ -155,7 +155,7 @@ int msi_init(struct PCIDevice *dev, uint8_t offset,
pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
if (msi_per_vector_mask) {
/* Make mask bits 0 to nr_vectors - 1 writeable. */
/* Make mask bits 0 to nr_vectors - 1 writable. */
pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
}

2
hw/msix.c
View File

@ -87,7 +87,7 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
bar_nr);
pdev->msix_cap = config_offset;
/* Make flags bit writeable. */
/* Make flags bit writable. */
pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
MSIX_MASKALL_MASK;
return 0;

2
hw/mst_fpga.c
View File

@ -154,7 +154,7 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
case MST_MSCRD:
s->mscrd = value;
break;
case MST_INTMSKENA: /* Mask interupt */
case MST_INTMSKENA: /* Mask interrupt */
s->intmskena = (value & 0xFEEFF);
qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
break;

6
hw/pci.c
View File

@ -168,7 +168,7 @@ void pci_device_reset(PCIDevice *dev)
dev->irq_state = 0;
pci_update_irq_status(dev);
pci_device_deassert_intx(dev);
/* Clear all writeable bits */
/* Clear all writable bits */
pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
pci_get_word(dev->wmask + PCI_COMMAND) |
pci_get_word(dev->w1cmask + PCI_COMMAND));
@ -871,7 +871,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
wmask = ~(size - 1);
addr = pci_bar(pci_dev, region_num);
if (region_num == PCI_ROM_SLOT) {
/* ROM enable bit is writeable */
/* ROM enable bit is writable */
wmask |= PCI_ROM_ADDRESS_ENABLE;
}
pci_set_long(pci_dev->config + addr, type);
@ -1977,7 +1977,7 @@ void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
if (!offset)
return;
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
/* Make capability writeable again */
/* Make capability writable again */
memset(pdev->wmask + offset, 0xff, size);
memset(pdev->w1cmask + offset, 0, size);
/* Clear cmask as device-specific registers can't be checked */

2
hw/pci.h
View File

@ -132,7 +132,7 @@ struct PCIDevice {
/* PCI config space */
uint8_t *config;
/* Used to enable config checks on load. Note that writeable bits are
/* Used to enable config checks on load. Note that writable bits are
* never checked even if set in cmask. */
uint8_t *cmask;

2
hw/pci_regs.h
View File

@ -223,7 +223,7 @@
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */

2
hw/pcie.c
View File

@ -176,7 +176,7 @@ static void hotplug_event_notify(PCIDevice *dev)
}
/*
* A PCI Express Hot-Plug Event has occured, so update slot status register
* A PCI Express Hot-Plug Event has occurred, so update slot status register
* and notify OS of the event if necessary.
*
* 6.7.3 PCI Express Hot-Plug Events

2
hw/pcie.h
View File

@ -40,7 +40,7 @@ typedef enum {
*
* Not all the bits of slot control register match with the ones of
* slot status. Not some bits of slot status register is used to
* show status, not to report event occurence.
* show status, not to report event occurrence.
* So such bits must be masked out when checking the software
* notification condition.
*/

2
hw/pcie_aer.c
View File

@ -612,7 +612,7 @@ static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal)
/*
* non-Function specific error must be recorded in all functions.
* It is the responsibility of the caller of this function.
* It is also caller's responsiblity to determine which function should
* It is also caller's responsibility to determine which function should
* report the rerror.
*
* 6.2.4 Error Logging

2
hw/pflash_cfi02.c
View File

@ -367,7 +367,7 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
case 4:
switch (pfl->cmd) {
case 0xA0:
/* Ignore writes while flash data write is occuring */
/* Ignore writes while flash data write is occurring */
/* As we suppose write is immediate, this should never happen */
return;
case 0x80:

2
hw/pl031.c
View File

@ -161,7 +161,7 @@ static void pl031_write(void * opaque, target_phys_addr_t offset,
pl031_update(s);
break;
case RTC_ICR:
/* The PL031 documentation (DDI0224B) states that the interupt is
/* The PL031 documentation (DDI0224B) states that the interrupt is
cleared when bit 0 of the written value is set. However the
arm926e documentation (DDI0287B) states that the interrupt is
cleared when any value is written. */

4
hw/pl061.c
View File

@ -98,7 +98,7 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
return s->isense;
case 0x408: /* Interrupt both edges */
return s->ibe;
case 0x40c: /* Interupt event */
case 0x40c: /* Interrupt event */
return s->iev;
case 0x410: /* Interrupt mask */
return s->im;
@ -156,7 +156,7 @@ static void pl061_write(void *opaque, target_phys_addr_t offset,
case 0x408: /* Interrupt both edges */
s->ibe = value;
break;
case 0x40c: /* Interupt event */
case 0x40c: /* Interrupt event */
s->iev = value;
break;
case 0x410: /* Interrupt mask */

2
hw/ppc4xx_devs.c
View File

@ -38,7 +38,7 @@
#endif
/*****************************************************************************/
/* Generic PowerPC 4xx processor instanciation */
/* Generic PowerPC 4xx processor instantiation */
CPUState *ppc4xx_init (const char *cpu_model,
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
uint32_t sysclk)

44
hw/rtl8139.c
View File

@ -1399,7 +1399,7 @@ static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
s->currCPlusTxDesc = 0;
}
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0xe3, s->bChipCmdState);
/* Deassert reset pin before next read */
@ -1443,7 +1443,7 @@ static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
s->cplus_enabled = 1;
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0xff84, s->CpCmd);
s->CpCmd = val;
@ -1472,7 +1472,7 @@ static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
return ret;
}
static int rtl8139_config_writeable(RTL8139State *s)
static int rtl8139_config_writable(RTL8139State *s)
{
if (s->Cfg9346 & Cfg9346_Unlock)
{
@ -1490,10 +1490,10 @@ static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
/* mask unwriteable bits */
/* mask unwritable bits */
uint32_t mask = 0x4cff;
if (1 || !rtl8139_config_writeable(s))
if (1 || !rtl8139_config_writable(s))
{
/* Speed setting and autonegotiation enable bits are read-only */
mask |= 0x3000;
@ -1521,7 +1521,7 @@ static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
s->BasicModeStatus = val;
@ -1542,7 +1542,7 @@ static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
DPRINTF("Cfg9346 write val=0x%02x\n", val);
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0x31, s->Cfg9346);
uint32_t opmode = val & 0xc0;
@ -1594,10 +1594,11 @@ static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
DPRINTF("Config0 write val=0x%02x\n", val);
if (!rtl8139_config_writeable(s))
if (!rtl8139_config_writable(s)) {
return;
}
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0xf8, s->Config0);
s->Config0 = val;
@ -1618,10 +1619,11 @@ static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
DPRINTF("Config1 write val=0x%02x\n", val);
if (!rtl8139_config_writeable(s))
if (!rtl8139_config_writable(s)) {
return;
}
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0xC, s->Config1);
s->Config1 = val;
@ -1642,10 +1644,11 @@ static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
DPRINTF("Config3 write val=0x%02x\n", val);
if (!rtl8139_config_writeable(s))
if (!rtl8139_config_writable(s)) {
return;
}
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0x8F, s->Config3);
s->Config3 = val;
@ -1666,10 +1669,11 @@ static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
DPRINTF("Config4 write val=0x%02x\n", val);
if (!rtl8139_config_writeable(s))
if (!rtl8139_config_writable(s)) {
return;
}
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0x0a, s->Config4);
s->Config4 = val;
@ -1690,7 +1694,7 @@ static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
DPRINTF("Config5 write val=0x%02x\n", val);
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0x80, s->Config5);
s->Config5 = val;
@ -1743,7 +1747,7 @@ static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
{
DPRINTF("RxConfig write val=0x%08x\n", val);
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
s->RxConfig = val;
@ -2610,7 +2614,7 @@ static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
{
DPRINTF("IntrMask write(w) val=0x%04x\n", val);
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0x1e00, s->IntrMask);
s->IntrMask = val;
@ -2642,7 +2646,7 @@ static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
#else
uint16_t newStatus = s->IntrStatus & ~val;
/* mask unwriteable bits */
/* mask unwritable bits */
newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
/* writing 1 to interrupt status register bit clears it */
@ -2686,7 +2690,7 @@ static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
{
DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
/* mask unwriteable bits */
/* mask unwritable bits */
val = SET_MASKED(val, 0xf000, s->MultiIntr);
s->MultiIntr = val;

6
hw/sh7750_regs.h
View File

@ -23,9 +23,9 @@
* All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
* in 0x1f000000 - 0x1fffffff (area 7 address)
*/
#define SH7750_P4_BASE 0xff000000 /* Accessable only in
priveleged mode */
#define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */
#define SH7750_P4_BASE 0xff000000 /* Accessible only in
privileged mode */
#define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))

2
hw/ssd0303.c
View File

@ -93,7 +93,7 @@ static int ssd0303_send(i2c_slave *i2c, uint8_t data)
DPRINTF("cmd 0x%02x\n", data);
s->mode = SSD0303_IDLE;
switch (data) {
case 0x00 ... 0x0f: /* Set lower colum address. */
case 0x00 ... 0x0f: /* Set lower column address. */
s->col = (s->col & 0xf0) | (data & 0xf);
break;
case 0x10 ... 0x20: /* Set higher column address. */

2
hw/sun4m_iommu.c
View File

@ -118,7 +118,7 @@
#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
Viking/MXCC) */
#define IOPTE_WRITE 0x00000004 /* Writeable */
#define IOPTE_WRITE 0x00000004 /* Writable */
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ 0x00000001 /* Write as zeros */

2
hw/syborg_serial.c
View File

@ -126,7 +126,7 @@ static void do_dma_tx(SyborgSerialState *s, uint32_t count)
s->dma_tx_ptr += count;
}
/* QEMU char backends do not have a nonblocking mode, so we transmit all
the data imediately and the interrupt status will be unchanged. */
the data immediately and the interrupt status will be unchanged. */
}
/* Initiate RX DMA, and transfer data from the FIFO. */

4
hw/xilinx_axidma.c
View File

@ -134,10 +134,10 @@ static inline int stream_idle(struct AXIStream *s)
static void stream_reset(struct AXIStream *s)
{
s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshhold. */
s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */
}
/* Mapp an offset addr into a channel index. */
/* Map an offset addr into a channel index. */
static inline int streamid_from_addr(target_phys_addr_t addr)
{
int sid;

9
libcacard/Makefile
View File

@ -4,14 +4,7 @@
$(call set-vpath, $(SRC_PATH):$(SRC_PATH)/libcacard)
ifeq ($(CONFIG_WIN32),y)
QEMU_THREAD=qemu-thread-win32.o
else
QEMU_THREAD=qemu-thread-posix.o
endif
QEMU_OBJS=$(addprefix ../, $(QEMU_THREAD) $(oslib-obj-y) $(trace-obj-y) qemu-malloc.o qemu-timer-common.o)
QEMU_OBJS=$(addprefix ../, $(oslib-obj-y) $(trace-obj-y) qemu-malloc.o qemu-timer-common.o)
QEMU_CFLAGS+=-I../

2
libcacard/vcard_emul_nss.c
View File

@ -971,7 +971,7 @@ find_blank(const char *str)
/*
* We really want to use some existing argument parsing library here. That
* would give us a consistant look */
* would give us a consistent look */
static VCardEmulOptions options;
#define READER_STEP 4

2
libcacard/vscard_common.h
View File

@ -153,7 +153,7 @@ typedef struct VSCMsgCardRemove {
/*
* VSCMsgAPDU Client <-> Host
* Main reason of existance. Transfer a single APDU in either direction.
* Main reason of existence. Transfer a single APDU in either direction.
*/
typedef struct VSCMsgAPDU {
uint8_t data[0];

2
linux-user/main.c
View File

@ -323,7 +323,7 @@ void cpu_loop(CPUX86State *env)
break;
#ifndef TARGET_ABI32
case EXCP_SYSCALL:
/* linux syscall from syscall intruction */
/* linux syscall from syscall instruction */
env->regs[R_EAX] = do_syscall(env,
env->regs[R_EAX],
env->regs[R_EDI],

2
linux-user/mmap.c
View File

@ -354,7 +354,7 @@ abi_ulong mmap_find_vma(abi_ulong start, abi_ulong size)
}
wrapped = 1;
/* Don't actually use 0 when wrapping, instead indicate
that we'd truely like an allocation in low memory. */
that we'd truly like an allocation in low memory. */
addr = (mmap_min_addr > TARGET_PAGE_SIZE
? TARGET_PAGE_ALIGN(mmap_min_addr)
: TARGET_PAGE_SIZE);

2
linux-user/qemu.h
View File

@ -379,7 +379,7 @@ abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len);
abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len);
/* Functions for accessing guest memory. The tget and tput functions
read/write single values, byteswapping as neccessary. The lock_user
read/write single values, byteswapping as necessary. The lock_user
gets a pointer to a contiguous area of guest memory, but does not perform
and byteswapping. lock_user may return either a pointer to the guest
memory, or a temporary buffer. */

2
linux-user/signal.c
View File

@ -391,7 +391,7 @@ static void QEMU_NORETURN force_sig(int target_sig)
target_sig, strsignal(host_sig), "core dumped" );
}
/* The proper exit code for dieing from an uncaught signal is
/* The proper exit code for dying from an uncaught signal is
* -<signal>. The kernel doesn't allow exit() or _exit() to pass
* a negative value. To get the proper exit code we need to
* actually die from an uncaught signal. Here the default signal

2
linux-user/syscall.c
View File

@ -287,7 +287,7 @@ static int sys_uname(struct new_utsname *buf)
* struct linux kernel uses).
*/
bzero(buf, sizeof (*buf));
memset(buf, 0, sizeof(*buf));
COPY_UTSNAME_FIELD(buf->sysname, uts_buf.sysname);
COPY_UTSNAME_FIELD(buf->nodename, uts_buf.nodename);
COPY_UTSNAME_FIELD(buf->release, uts_buf.release);

10
target-arm/translate.c
View File

@ -1331,7 +1331,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
return 0;
}
/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
{
@ -2335,7 +2335,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
return 0;
}
/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
/* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
{
@ -2681,7 +2681,7 @@ static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size)
return tmp;
}
/* Disassemble a VFP instruction. Returns nonzero if an error occured
/* Disassemble a VFP instruction. Returns nonzero if an error occurred
(ie. an undefined instruction). */
static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
{
@ -7348,7 +7348,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
} else if ((insn & 0x000003e0) == 0x00000060) {
tmp = load_reg(s, rm);
shift = (insn >> 10) & 3;
/* ??? In many cases it's not neccessary to do a
/* ??? In many cases it's not necessary to do a
rotate, a shift is sufficient. */
if (shift != 0)
tcg_gen_rotri_i32(tmp, tmp, shift * 8);
@ -8139,7 +8139,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
case 1: /* Sign/zero extend. */
tmp = load_reg(s, rm);
shift = (insn >> 4) & 3;
/* ??? In many cases it's not neccessary to do a
/* ??? In many cases it's not necessary to do a
rotate, a shift is sufficient. */
if (shift != 0)
tcg_gen_rotri_i32(tmp, tmp, shift * 8);

2
target-cris/cpu.h
View File

@ -104,7 +104,7 @@ typedef struct CPUCRISState {
/* P0 - P15 are referred to as special registers in the docs. */
uint32_t pregs[16];
/* Pseudo register for the PC. Not directly accessable on CRIS. */
/* Pseudo register for the PC. Not directly accessible on CRIS. */
uint32_t pc;
/* Pseudo register for the kernel stack. */

2
target-cris/translate_v10.c
View File

@ -956,7 +956,7 @@ static int dec10_bdap_m(DisasContext *dc, int size)
return insn_len;
}
#endif
/* Now the rest of the modes are truely indirect. */
/* Now the rest of the modes are truly indirect. */
insn_len += dec10_prep_move_m(dc, 1, size, cpu_PR[PR_PREFIX]);
tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_PR[PR_PREFIX], cpu_R[rd]);
cris_set_prefix(dc);

2
target-m68k/helper.c
View File

@ -714,7 +714,7 @@ void HELPER(macsats)(CPUState *env, uint32_t acc)
if (env->macsr & MACSR_V) {
env->macsr |= MACSR_PAV0 << acc;
if (env->macsr & MACSR_OMC) {
/* The result is saturated to 32 bits, despite overflow occuring
/* The result is saturated to 32 bits, despite overflow occurring
at 48 bits. Seems weird, but that's what the hardware docs
say. */
result = (result >> 63) ^ 0x7fffffff;

2
target-microblaze/helper.c
View File

@ -117,7 +117,7 @@ void do_interrupt(CPUState *env)
{
uint32_t t;
/* IMM flag cannot propagate accross a branch and into the dslot. */
/* IMM flag cannot propagate across a branch and into the dslot. */
assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */

4
target-mips/translate_init.c
View File

@ -38,7 +38,7 @@
((1 << CP0C2_M))
/* No config4, no DSP ASE, no large physaddr (PABITS),
no external interrupt controller, no vectored interupts,
no external interrupt controller, no vectored interrupts,
no 1kb pages, no SmartMIPS ASE, no trace logic */
#define MIPS_CONFIG3 \
((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
@ -477,7 +477,7 @@ static const mips_def_t mips_defs[] =
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.SYNCI_Step = 16,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/
.CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
.SEGBITS = 40,
.PABITS = 40,

2
target-ppc/cpu.h
View File

@ -225,7 +225,7 @@ enum {
/* 970FX specific exceptions */
POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
/* Freescale embeded cores specific exceptions */
/* Freescale embedded cores specific exceptions */
POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */

2
target-ppc/translate_init.c
View File

@ -9049,7 +9049,7 @@ static const ppc_def_t ppc_defs[] = {
};
/*****************************************************************************/
/* Generic CPU instanciation routine */
/* Generic CPU instantiation routine */
static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
{
#if !defined(CONFIG_USER_ONLY)

4
tcg/tcg.h
View File

@ -252,9 +252,9 @@ typedef struct TCGTemp {
unsigned int fixed_reg:1;
unsigned int mem_coherent:1;
unsigned int mem_allocated:1;
unsigned int temp_local:1; /* If true, the temp is saved accross
unsigned int temp_local:1; /* If true, the temp is saved across
basic blocks. Otherwise, it is not
preserved accross basic blocks. */
preserved across basic blocks. */
unsigned int temp_allocated:1; /* never used for code gen */
/* index of next free temp of same base type, -1 if end */
int next_free_temp;

2
tests/test-i386.c
View File

@ -2281,7 +2281,7 @@ void test_sse_comi(double a1, double b1)
}
/* Force %xmm0 usage to avoid the case where both register index are 0
to test intruction decoding more extensively */
to test instruction decoding more extensively */
#define CVT_OP_XMM2MMX(op)\
{\
asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \

4
tests/test-mmap.c
View File

@ -322,7 +322,7 @@ void check_file_unfixed_eof_mmaps(void)
fail_unless (p1[(test_fsize & pagemask) / sizeof *p1 - 1]
== ((test_fsize - sizeof *p1) / sizeof *p1));
/* Verify that the end of page is accessable and zeroed. */
/* Verify that the end of page is accessible and zeroed. */
cp = (void *) p1;
fail_unless (cp[pagesize - 4] == 0);
munmap (p1, pagesize);
@ -365,7 +365,7 @@ void check_file_fixed_eof_mmaps(void)
fail_unless (p1[(test_fsize & pagemask) / sizeof *p1 - 1]
== ((test_fsize - sizeof *p1) / sizeof *p1));
/* Verify that the end of page is accessable and zeroed. */
/* Verify that the end of page is accessible and zeroed. */
cp = (void *)p1;
fail_unless (cp[pagesize - 4] == 0);
munmap (p1, pagesize);