tcg/arm: Split out constraint sets to tcg-target-con-set.h
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson
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35
tcg/arm/tcg-target-con-set.h
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35
tcg/arm/tcg-target-con-set.h
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@ -0,0 +1,35 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define Arm target-specific constraint sets.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
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* Each operand should be a sequence of constraint letters as defined by
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I1(r)
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C_O0_I2(r, r)
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C_O0_I2(r, rIN)
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C_O0_I2(s, s)
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C_O0_I3(s, s, s)
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C_O0_I4(r, r, rI, rI)
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C_O0_I4(s, s, s, s)
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C_O1_I1(r, l)
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C_O1_I1(r, r)
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C_O1_I2(r, 0, rZ)
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C_O1_I2(r, l, l)
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C_O1_I2(r, r, r)
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C_O1_I2(r, r, rI)
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C_O1_I2(r, r, rIK)
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C_O1_I2(r, r, rIN)
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C_O1_I2(r, r, ri)
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C_O1_I2(r, rZ, rZ)
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C_O1_I4(r, r, r, rI, rI)
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C_O1_I4(r, r, rIN, rIK, 0)
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C_O2_I1(r, r, l)
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C_O2_I2(r, r, l, l)
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C_O2_I2(r, r, r, r)
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C_O2_I4(r, r, r, r, rIN, rIK)
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C_O2_I4(r, r, rI, rI, rIN, rIK)
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@ -2036,57 +2036,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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}
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static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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{
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static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
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static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
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static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
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static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
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static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
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static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
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static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
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static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
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static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
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static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
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static const TCGTargetOpDef r_r_rIN
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= { .args_ct_str = { "r", "r", "rIN" } };
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static const TCGTargetOpDef r_r_rIK
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= { .args_ct_str = { "r", "r", "rIK" } };
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static const TCGTargetOpDef r_r_r_r
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= { .args_ct_str = { "r", "r", "r", "r" } };
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static const TCGTargetOpDef r_r_l_l
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= { .args_ct_str = { "r", "r", "l", "l" } };
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static const TCGTargetOpDef s_s_s_s
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= { .args_ct_str = { "s", "s", "s", "s" } };
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static const TCGTargetOpDef br
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= { .args_ct_str = { "r", "rIN" } };
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static const TCGTargetOpDef ext2
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= { .args_ct_str = { "r", "rZ", "rZ" } };
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static const TCGTargetOpDef dep
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= { .args_ct_str = { "r", "0", "rZ" } };
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static const TCGTargetOpDef movc
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= { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
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static const TCGTargetOpDef add2
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= { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
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static const TCGTargetOpDef sub2
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= { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
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static const TCGTargetOpDef br2
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= { .args_ct_str = { "r", "r", "rI", "rI" } };
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static const TCGTargetOpDef setc2
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= { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
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switch (op) {
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case INDEX_op_goto_ptr:
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return &r;
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return C_O0_I1(r);
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case INDEX_op_ld8u_i32:
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case INDEX_op_ld8s_i32:
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case INDEX_op_ld16u_i32:
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case INDEX_op_ld16s_i32:
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case INDEX_op_ld_i32:
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case INDEX_op_st8_i32:
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case INDEX_op_st16_i32:
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case INDEX_op_st_i32:
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case INDEX_op_neg_i32:
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case INDEX_op_not_i32:
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case INDEX_op_bswap16_i32:
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@ -2096,62 +2056,72 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_ext16u_i32:
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case INDEX_op_extract_i32:
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case INDEX_op_sextract_i32:
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return &r_r;
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return C_O1_I1(r, r);
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case INDEX_op_st8_i32:
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case INDEX_op_st16_i32:
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case INDEX_op_st_i32:
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return C_O0_I2(r, r);
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case INDEX_op_add_i32:
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case INDEX_op_sub_i32:
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case INDEX_op_setcond_i32:
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return &r_r_rIN;
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return C_O1_I2(r, r, rIN);
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case INDEX_op_and_i32:
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case INDEX_op_andc_i32:
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case INDEX_op_clz_i32:
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case INDEX_op_ctz_i32:
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return &r_r_rIK;
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return C_O1_I2(r, r, rIK);
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case INDEX_op_mul_i32:
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case INDEX_op_div_i32:
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case INDEX_op_divu_i32:
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return &r_r_r;
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return C_O1_I2(r, r, r);
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case INDEX_op_mulu2_i32:
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case INDEX_op_muls2_i32:
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return &r_r_r_r;
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return C_O2_I2(r, r, r, r);
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case INDEX_op_or_i32:
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case INDEX_op_xor_i32:
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return &r_r_rI;
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return C_O1_I2(r, r, rI);
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case INDEX_op_shl_i32:
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case INDEX_op_shr_i32:
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case INDEX_op_sar_i32:
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case INDEX_op_rotl_i32:
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case INDEX_op_rotr_i32:
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return &r_r_ri;
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return C_O1_I2(r, r, ri);
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case INDEX_op_brcond_i32:
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return &br;
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return C_O0_I2(r, rIN);
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case INDEX_op_deposit_i32:
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return &dep;
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return C_O1_I2(r, 0, rZ);
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case INDEX_op_extract2_i32:
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return &ext2;
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return C_O1_I2(r, rZ, rZ);
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case INDEX_op_movcond_i32:
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return &movc;
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return C_O1_I4(r, r, rIN, rIK, 0);
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case INDEX_op_add2_i32:
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return &add2;
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return C_O2_I4(r, r, r, r, rIN, rIK);
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case INDEX_op_sub2_i32:
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return &sub2;
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return C_O2_I4(r, r, rI, rI, rIN, rIK);
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case INDEX_op_brcond2_i32:
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return &br2;
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return C_O0_I4(r, r, rI, rI);
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case INDEX_op_setcond2_i32:
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return &setc2;
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return C_O1_I4(r, r, r, rI, rI);
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case INDEX_op_qemu_ld_i32:
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return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
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return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l);
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case INDEX_op_qemu_ld_i64:
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return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
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return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l);
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case INDEX_op_qemu_st_i32:
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return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
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return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s);
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case INDEX_op_qemu_st_i64:
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return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
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return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
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default:
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return NULL;
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g_assert_not_reached();
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}
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}
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@ -142,5 +142,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
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#define TCG_TARGET_NEED_LDST_LABELS
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#endif
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#define TCG_TARGET_NEED_POOL_LABELS
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#define TCG_TARGET_CON_SET_H
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#endif
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