target/i386: Add CHECK_NO_VEX
Reject invalid VEX encodings on MMX instructions. Signed-off-by: Paul Brook <paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220424220204.2493824-7-paul@nowt.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -3186,6 +3186,12 @@ static const struct SSEOpHelper_table7 sse_op_table7[256] = {
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#undef BLENDV_OP
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#undef SPECIAL_OP
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/* VEX prefix not allowed */
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#define CHECK_NO_VEX(s) do { \
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if (s->prefix & PREFIX_VEX) \
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goto illegal_op; \
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} while (0)
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static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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target_ulong pc_start)
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{
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@ -3272,6 +3278,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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b |= (b1 << 8);
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switch(b) {
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case 0x0e7: /* movntq */
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CHECK_NO_VEX(s);
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if (mod == 3) {
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goto illegal_op;
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}
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@ -3307,6 +3314,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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}
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break;
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case 0x6e: /* movd mm, ea */
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CHECK_NO_VEX(s);
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#ifdef TARGET_X86_64
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if (s->dflag == MO_64) {
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gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 0);
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@ -3338,6 +3346,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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}
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break;
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case 0x6f: /* movq mm, ea */
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CHECK_NO_VEX(s);
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if (mod != 3) {
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gen_lea_modrm(env, s, modrm);
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gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
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@ -3473,6 +3482,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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break;
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case 0x178:
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case 0x378:
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CHECK_NO_VEX(s);
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{
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int bit_index, field_length;
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@ -3492,6 +3502,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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}
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break;
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case 0x7e: /* movd ea, mm */
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CHECK_NO_VEX(s);
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#ifdef TARGET_X86_64
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if (s->dflag == MO_64) {
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tcg_gen_ld_i64(s->T0, cpu_env,
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@ -3532,6 +3543,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_op_movq_env_0(s, offsetof(CPUX86State, xmm_regs[reg].ZMM_Q(1)));
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break;
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case 0x7f: /* movq ea, mm */
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CHECK_NO_VEX(s);
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if (mod != 3) {
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gen_lea_modrm(env, s, modrm);
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gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx));
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@ -3614,6 +3626,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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offsetof(CPUX86State, xmm_t0.ZMM_L(1)));
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op1_offset = offsetof(CPUX86State,xmm_t0);
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} else {
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CHECK_NO_VEX(s);
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tcg_gen_movi_tl(s->T0, val);
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tcg_gen_st32_tl(s->T0, cpu_env,
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offsetof(CPUX86State, mmx_t0.MMX_L(0)));
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@ -3653,6 +3666,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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break;
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case 0x02a: /* cvtpi2ps */
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case 0x12a: /* cvtpi2pd */
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CHECK_NO_VEX(s);
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gen_helper_enter_mmx(cpu_env);
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if (mod != 3) {
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gen_lea_modrm(env, s, modrm);
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@ -3698,6 +3712,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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case 0x12c: /* cvttpd2pi */
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case 0x02d: /* cvtps2pi */
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case 0x12d: /* cvtpd2pi */
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CHECK_NO_VEX(s);
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gen_helper_enter_mmx(cpu_env);
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if (mod != 3) {
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gen_lea_modrm(env, s, modrm);
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@ -3771,6 +3786,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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tcg_gen_st16_tl(s->T0, cpu_env,
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offsetof(CPUX86State,xmm_regs[reg].ZMM_W(val)));
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} else {
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CHECK_NO_VEX(s);
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val &= 3;
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tcg_gen_st16_tl(s->T0, cpu_env,
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offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
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@ -3810,6 +3826,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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}
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break;
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case 0x2d6: /* movq2dq */
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CHECK_NO_VEX(s);
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gen_helper_enter_mmx(cpu_env);
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rm = (modrm & 7);
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gen_op_movq(s, offsetof(CPUX86State, xmm_regs[reg].ZMM_Q(0)),
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@ -3817,6 +3834,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_op_movq_env_0(s, offsetof(CPUX86State, xmm_regs[reg].ZMM_Q(1)));
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break;
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case 0x3d6: /* movdq2q */
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CHECK_NO_VEX(s);
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gen_helper_enter_mmx(cpu_env);
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rm = (modrm & 7) | REX_B(s);
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gen_op_movq(s, offsetof(CPUX86State, fpregs[reg & 7].mmx),
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@ -3831,6 +3849,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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tcg_gen_addi_ptr(s->ptr0, cpu_env, ZMM_OFFSET(rm));
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gen_helper_pmovmskb_xmm(s->tmp2_i32, cpu_env, s->ptr0);
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} else {
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CHECK_NO_VEX(s);
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rm = (modrm & 7);
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tcg_gen_addi_ptr(s->ptr0, cpu_env,
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offsetof(CPUX86State, fpregs[rm].mmx));
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@ -3901,6 +3920,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
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op6->fn[b1].op1(cpu_env, s->ptr0, s->ptr1);
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} else {
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CHECK_NO_VEX(s);
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if ((op6->flags & SSE_OPF_MMX) == 0) {
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goto unknown_op;
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}
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@ -3934,6 +3954,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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case 0x3f0: /* crc32 Gd,Eb */
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case 0x3f1: /* crc32 Gd,Ey */
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do_crc32:
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CHECK_NO_VEX(s);
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if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) {
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goto illegal_op;
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}
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@ -3956,6 +3977,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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case 0x1f0: /* crc32 or movbe */
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case 0x1f1:
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CHECK_NO_VEX(s);
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/* For these insns, the f3 prefix is supposed to have priority
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over the 66 prefix, but that's not what we implement above
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setting b1. */
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@ -3965,6 +3987,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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/* FALLTHRU */
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case 0x0f0: /* movbe Gy,My */
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case 0x0f1: /* movbe My,Gy */
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CHECK_NO_VEX(s);
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if (!(s->cpuid_ext_features & CPUID_EXT_MOVBE)) {
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goto illegal_op;
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}
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@ -4131,6 +4154,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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case 0x1f6: /* adcx Gy, Ey */
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case 0x2f6: /* adox Gy, Ey */
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CHECK_NO_VEX(s);
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if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX)) {
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goto illegal_op;
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} else {
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@ -4436,6 +4460,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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}
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if (b1 == 0) {
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CHECK_NO_VEX(s);
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/* MMX */
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if ((op7->flags & SSE_OPF_MMX) == 0) {
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goto illegal_op;
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@ -4582,6 +4607,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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op2_offset = ZMM_OFFSET(rm);
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}
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} else {
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CHECK_NO_VEX(s);
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op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
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if (mod != 3) {
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gen_lea_modrm(env, s, modrm);
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