target-arm: A64: add support for logical (immediate) insns
This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder, function renaming,
removed a TCG temp variable]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
[PMM: cleaned up some unnecessary code in logic_imm_decode_wmask
and added clarifying commentary on what it's actually doing.
Dropped an ext32u that's not needed if we've just done an AND.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Alexander Graf
Peter Maydell
parent
e80c502023
commit
71b4608930
@ -201,6 +201,21 @@ static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
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return t;
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}
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/*
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* Register access functions
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*
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* These functions are used for directly accessing a register in where
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* changes to the final register value are likely to be made. If you
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* need to use a register for temporary calculation (e.g. index type
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* operations) use the read_* form.
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*
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* B1.2.1 Register mappings
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*
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* In instruction register encoding 31 can refer to ZR (zero register) or
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* the SP (stack pointer) depending on context. In QEMU's case we map SP
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* to cpu_X[31] and ZR accesses to a temporary which can be discarded.
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* This is the point of the _sp forms.
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*/
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static TCGv_i64 cpu_reg(DisasContext *s, int reg)
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{
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if (reg == 31) {
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@ -210,6 +225,12 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg)
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}
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}
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/* register access for when 31 == SP */
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static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
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{
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return cpu_X[reg];
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}
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/* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
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* representing the register contents. This TCGv is an auto-freed
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* temporary so it need not be explicitly freed, and may be modified.
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@ -686,10 +707,160 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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}
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/* Logical (immediate) */
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/* The input should be a value in the bottom e bits (with higher
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* bits zero); returns that value replicated into every element
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* of size e in a 64 bit integer.
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*/
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static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
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{
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assert(e != 0);
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while (e < 64) {
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mask |= mask << e;
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e *= 2;
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}
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return mask;
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}
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/* Return a value with the bottom len bits set (where 0 < len <= 64) */
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static inline uint64_t bitmask64(unsigned int length)
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{
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assert(length > 0 && length <= 64);
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return ~0ULL >> (64 - length);
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}
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/* Simplified variant of pseudocode DecodeBitMasks() for the case where we
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* only require the wmask. Returns false if the imms/immr/immn are a reserved
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* value (ie should cause a guest UNDEF exception), and true if they are
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* valid, in which case the decoded bit pattern is written to result.
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*/
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static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
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unsigned int imms, unsigned int immr)
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{
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uint64_t mask;
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unsigned e, levels, s, r;
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int len;
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assert(immn < 2 && imms < 64 && immr < 64);
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/* The bit patterns we create here are 64 bit patterns which
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* are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
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* 64 bits each. Each element contains the same value: a run
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* of between 1 and e-1 non-zero bits, rotated within the
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* element by between 0 and e-1 bits.
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*
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* The element size and run length are encoded into immn (1 bit)
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* and imms (6 bits) as follows:
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* 64 bit elements: immn = 1, imms = <length of run - 1>
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* 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
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* 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
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* 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
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* 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
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* 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
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* Notice that immn = 0, imms = 11111x is the only combination
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* not covered by one of the above options; this is reserved.
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* Further, <length of run - 1> all-ones is a reserved pattern.
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*
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* In all cases the rotation is by immr % e (and immr is 6 bits).
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*/
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/* First determine the element size */
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len = 31 - clz32((immn << 6) | (~imms & 0x3f));
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if (len < 1) {
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/* This is the immn == 0, imms == 0x11111x case */
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return false;
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}
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e = 1 << len;
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levels = e - 1;
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s = imms & levels;
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r = immr & levels;
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if (s == levels) {
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/* <length of run - 1> mustn't be all-ones. */
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return false;
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}
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/* Create the value of one element: s+1 set bits rotated
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* by r within the element (which is e bits wide)...
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*/
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mask = bitmask64(s + 1);
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mask = (mask >> r) | (mask << (e - r));
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/* ...then replicate the element over the whole 64 bit value */
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mask = bitfield_replicate(mask, e);
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*result = mask;
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return true;
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}
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/* C3.4.4 Logical (immediate)
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* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
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* +----+-----+-------------+---+------+------+------+------+
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* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
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* +----+-----+-------------+---+------+------+------+------+
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*/
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static void disas_logic_imm(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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unsigned int sf, opc, is_n, immr, imms, rn, rd;
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TCGv_i64 tcg_rd, tcg_rn;
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uint64_t wmask;
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bool is_and = false;
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sf = extract32(insn, 31, 1);
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opc = extract32(insn, 29, 2);
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is_n = extract32(insn, 22, 1);
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immr = extract32(insn, 16, 6);
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imms = extract32(insn, 10, 6);
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rn = extract32(insn, 5, 5);
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rd = extract32(insn, 0, 5);
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if (!sf && is_n) {
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unallocated_encoding(s);
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return;
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}
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if (opc == 0x3) { /* ANDS */
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tcg_rd = cpu_reg(s, rd);
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} else {
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tcg_rd = cpu_reg_sp(s, rd);
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}
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tcg_rn = cpu_reg(s, rn);
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if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
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/* some immediate field values are reserved */
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unallocated_encoding(s);
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return;
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}
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if (!sf) {
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wmask &= 0xffffffff;
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}
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switch (opc) {
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case 0x3: /* ANDS */
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case 0x0: /* AND */
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tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
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is_and = true;
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break;
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case 0x1: /* ORR */
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tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
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break;
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case 0x2: /* EOR */
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tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
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break;
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default:
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assert(FALSE); /* must handle all above */
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break;
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}
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if (!sf && !is_and) {
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/* zero extend final result; we know we can skip this for AND
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* since the immediate had the high 32 bits clear.
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*/
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tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
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}
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if (opc == 3) { /* ANDS */
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gen_logic_CC(sf, tcg_rd);
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}
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}
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/* Move wide (immediate) */
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