target/sparc: Use tlb_set_page_full
Pass CPUTLBEntryFull to get_physical_address instead of a collection of pointers. Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
968f305e08
commit
71b7794bbe
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@ -64,10 +64,9 @@ static const int perm_table[2][8] = {
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}
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};
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static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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int *prot, int *access_index, MemTxAttrs *attrs,
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target_ulong address, int rw, int mmu_idx,
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target_ulong *page_size)
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static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
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int *access_index, target_ulong address,
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int rw, int mmu_idx)
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{
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int access_perms = 0;
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hwaddr pde_ptr;
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@ -80,20 +79,20 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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is_user = mmu_idx == MMU_USER_IDX;
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if (mmu_idx == MMU_PHYS_IDX) {
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*page_size = TARGET_PAGE_SIZE;
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full->lg_page_size = TARGET_PAGE_BITS;
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/* Boot mode: instruction fetches are taken from PROM */
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if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) {
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC;
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full->phys_addr = env->prom_addr | (address & 0x7ffffULL);
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full->prot = PAGE_READ | PAGE_EXEC;
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return 0;
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}
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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full->phys_addr = address;
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full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
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*physical = 0xffffffffffff0000ULL;
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full->phys_addr = 0xffffffffffff0000ULL;
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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@ -157,16 +156,17 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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case 2: /* L3 PTE */
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page_offset = 0;
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}
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*page_size = TARGET_PAGE_SIZE;
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full->lg_page_size = TARGET_PAGE_BITS;
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break;
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case 2: /* L2 PTE */
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page_offset = address & 0x3f000;
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*page_size = 0x40000;
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full->lg_page_size = 18;
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}
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break;
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case 2: /* L1 PTE */
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page_offset = address & 0xfff000;
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*page_size = 0x1000000;
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full->lg_page_size = 24;
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break;
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}
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}
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@ -188,16 +188,16 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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}
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms];
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full->prot = perm_table[is_user][access_perms];
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE;
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full->prot &= ~PAGE_WRITE;
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}
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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full->phys_addr = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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}
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@ -208,11 +208,9 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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hwaddr paddr;
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CPUTLBEntryFull full = {};
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target_ulong vaddr;
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target_ulong page_size;
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int error_code = 0, prot, access_index;
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MemTxAttrs attrs = {};
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int error_code = 0, access_index;
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/*
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* TODO: If we ever need tlb_vaddr_to_host for this target,
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@ -223,16 +221,15 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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assert(!probe);
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address &= TARGET_PAGE_MASK;
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error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
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address, access_type,
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mmu_idx, &page_size);
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error_code = get_physical_address(env, &full, &access_index,
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address, access_type, mmu_idx);
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vaddr = address;
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if (likely(error_code == 0)) {
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qemu_log_mask(CPU_LOG_MMU,
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"Translate at %" VADDR_PRIx " -> "
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HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
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address, paddr, vaddr);
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tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
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address, full.phys_addr, vaddr);
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tlb_set_page_full(cs, mmu_idx, vaddr, &full);
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return true;
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}
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@ -247,8 +244,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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permissions. If no mapping is available, redirect accesses to
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neverland. Fake/overridden mappings will be flushed when
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switching to normal mode. */
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
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full.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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tlb_set_page_full(cs, mmu_idx, vaddr, &full);
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return true;
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} else {
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if (access_type == MMU_INST_FETCH) {
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@ -545,8 +542,7 @@ static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw)
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return sfsr;
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}
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static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
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int *prot, MemTxAttrs *attrs,
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static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full,
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target_ulong address, int rw, int mmu_idx)
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{
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CPUState *cs = env_cpu(env);
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@ -579,11 +575,12 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
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for (i = 0; i < 64; i++) {
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/* ctx match, vaddr match, valid? */
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if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
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if (ultrasparc_tag_match(&env->dtlb[i], address, context,
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&full->phys_addr)) {
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int do_fault = 0;
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if (TTE_IS_IE(env->dtlb[i].tte)) {
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attrs->byte_swap = true;
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full->attrs.byte_swap = true;
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}
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/* access ok? */
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@ -616,9 +613,9 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
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}
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if (!do_fault) {
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*prot = PAGE_READ;
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full->prot = PAGE_READ;
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if (TTE_IS_W_OK(env->dtlb[i].tte)) {
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*prot |= PAGE_WRITE;
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full->prot |= PAGE_WRITE;
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}
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TTE_SET_USED(env->dtlb[i].tte);
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@ -645,8 +642,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
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return 1;
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}
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static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
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int *prot, MemTxAttrs *attrs,
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static int get_physical_address_code(CPUSPARCState *env, CPUTLBEntryFull *full,
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target_ulong address, int mmu_idx)
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{
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CPUState *cs = env_cpu(env);
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@ -681,7 +677,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
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for (i = 0; i < 64; i++) {
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/* ctx match, vaddr match, valid? */
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if (ultrasparc_tag_match(&env->itlb[i],
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address, context, physical)) {
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address, context, &full->phys_addr)) {
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/* access ok? */
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if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
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/* Fault status register */
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@ -708,7 +704,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
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return 1;
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}
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*prot = PAGE_EXEC;
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full->prot = PAGE_EXEC;
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TTE_SET_USED(env->itlb[i].tte);
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return 0;
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}
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@ -722,14 +718,13 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
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return 1;
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}
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static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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int *prot, int *access_index, MemTxAttrs *attrs,
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target_ulong address, int rw, int mmu_idx,
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target_ulong *page_size)
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static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
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int *access_index, target_ulong address,
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int rw, int mmu_idx)
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{
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/* ??? We treat everything as a small page, then explicitly flush
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everything when an entry is evicted. */
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*page_size = TARGET_PAGE_SIZE;
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full->lg_page_size = TARGET_PAGE_BITS;
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/* safety net to catch wrong softmmu index use from dynamic code */
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if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
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@ -747,17 +742,15 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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}
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if (mmu_idx == MMU_PHYS_IDX) {
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*physical = ultrasparc_truncate_physical(address);
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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full->phys_addr = ultrasparc_truncate_physical(address);
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full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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if (rw == 2) {
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return get_physical_address_code(env, physical, prot, attrs, address,
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mmu_idx);
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return get_physical_address_code(env, full, address, mmu_idx);
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} else {
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return get_physical_address_data(env, physical, prot, attrs, address,
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rw, mmu_idx);
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return get_physical_address_data(env, full, address, rw, mmu_idx);
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}
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}
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@ -768,25 +761,17 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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target_ulong vaddr;
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hwaddr paddr;
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target_ulong page_size;
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MemTxAttrs attrs = {};
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int error_code = 0, prot, access_index;
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CPUTLBEntryFull full = {};
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int error_code = 0, access_index;
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address &= TARGET_PAGE_MASK;
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error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
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address, access_type,
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mmu_idx, &page_size);
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error_code = get_physical_address(env, &full, &access_index,
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address, access_type, mmu_idx);
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if (likely(error_code == 0)) {
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vaddr = address;
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trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
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trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->tl,
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env->dmmu.mmu_primary_context,
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env->dmmu.mmu_secondary_context);
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tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,
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page_size);
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tlb_set_page_full(cs, mmu_idx, address, &full);
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return true;
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}
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if (probe) {
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@ -888,12 +873,14 @@ void dump_mmu(CPUSPARCState *env)
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static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
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target_ulong addr, int rw, int mmu_idx)
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{
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target_ulong page_size;
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int prot, access_index;
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MemTxAttrs attrs = {};
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CPUTLBEntryFull full = {};
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int access_index, ret;
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return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
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rw, mmu_idx, &page_size);
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ret = get_physical_address(env, &full, &access_index, addr, rw, mmu_idx);
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if (ret == 0) {
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*phys = full.phys_addr;
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}
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return ret;
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}
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#if defined(TARGET_SPARC64)
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