hw/ppc/ppc405_uc: Drop use of ppcuic_init()
Switch the ppc405_uc boards to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. We retain the API feature of ppc405ep_init() where it passes back something allowing the callers to wire up devices to the UIC if they need to, even though neither of the callsites currently makes use of this ability -- instead of passing back the qemu_irq array we pass back the UIC DeviceState. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421922 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210108171212.16500-4-peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Peter Maydell
David Gibson
parent
37dc4b5f7c
commit
71c3c44bc3
@ -66,7 +66,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
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MemoryRegion ram_memories[2],
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hwaddr ram_bases[2],
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hwaddr ram_sizes[2],
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uint32_t sysclk, qemu_irq **picp,
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uint32_t sysclk, DeviceState **uicdev,
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int do_init);
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#endif /* PPC405_H */
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@ -151,7 +151,6 @@ static void ref405ep_init(MachineState *machine)
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CPUPPCState *env;
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DeviceState *dev;
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SysBusDevice *s;
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qemu_irq *pic;
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MemoryRegion *bios;
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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ram_addr_t bdloc;
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@ -167,6 +166,7 @@ static void ref405ep_init(MachineState *machine)
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int len;
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DriveInfo *dinfo;
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MemoryRegion *sysmem = get_system_memory();
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DeviceState *uicdev;
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if (machine->ram_size != mc->default_ram_size) {
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char *sz = size_to_str(mc->default_ram_size);
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@ -184,7 +184,7 @@ static void ref405ep_init(MachineState *machine)
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ram_bases[1] = 0x00000000;
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ram_sizes[1] = 0x00000000;
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env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
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33333333, &pic, kernel_filename == NULL ? 0 : 1);
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33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
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/* allocate SRAM */
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sram_size = 512 * KiB;
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memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
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@ -429,7 +429,6 @@ static void taihu_405ep_init(MachineState *machine)
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const char *kernel_filename = machine->kernel_filename;
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const char *initrd_filename = machine->initrd_filename;
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char *filename;
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qemu_irq *pic;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *bios;
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MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
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@ -440,6 +439,7 @@ static void taihu_405ep_init(MachineState *machine)
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int linux_boot;
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int fl_idx;
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DriveInfo *dinfo;
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DeviceState *uicdev;
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if (machine->ram_size != mc->default_ram_size) {
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char *sz = size_to_str(mc->default_ram_size);
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@ -459,7 +459,7 @@ static void taihu_405ep_init(MachineState *machine)
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"taihu_405ep.ram-1", machine->ram, ram_bases[1],
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ram_sizes[1]);
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ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
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33333333, &pic, kernel_filename == NULL ? 0 : 1);
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33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
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/* allocate and load BIOS */
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fl_idx = 0;
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#if defined(USE_FLASH_BIOS)
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@ -36,6 +36,9 @@
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#include "sysemu/sysemu.h"
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#include "qemu/log.h"
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#include "exec/address-spaces.h"
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#include "hw/intc/ppc-uic.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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//#define DEBUG_OPBA
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//#define DEBUG_SDRAM
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@ -1446,14 +1449,15 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
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MemoryRegion ram_memories[2],
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hwaddr ram_bases[2],
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hwaddr ram_sizes[2],
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uint32_t sysclk, qemu_irq **picp,
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uint32_t sysclk, DeviceState **uicdevp,
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int do_init)
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{
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clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
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qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
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PowerPCCPU *cpu;
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CPUPPCState *env;
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qemu_irq *pic, *irqs;
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DeviceState *uicdev;
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SysBusDevice *uicsbd;
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memset(clk_setup, 0, sizeof(clk_setup));
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/* init CPUs */
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@ -1474,59 +1478,69 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
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/* Initialize timers */
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ppc_booke_timers_init(cpu, sysclk, 0);
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/* Universal interrupt controller */
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irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] =
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((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] =
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((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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*picp = pic;
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uicdev = qdev_new(TYPE_PPC_UIC);
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uicsbd = SYS_BUS_DEVICE(uicdev);
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object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
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&error_fatal);
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sysbus_realize_and_unref(uicsbd, &error_fatal);
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sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
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((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
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sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
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((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
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*uicdevp = uicdev;
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/* SDRAM controller */
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/* XXX 405EP has no ECC interrupt */
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ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
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ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
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ram_bases, ram_sizes, do_init);
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/* External bus controller */
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ppc405_ebc_init(env);
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/* DMA controller */
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dma_irqs[0] = pic[5];
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dma_irqs[1] = pic[6];
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dma_irqs[2] = pic[7];
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dma_irqs[3] = pic[8];
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dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
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dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
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dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
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dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
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ppc405_dma_init(env, dma_irqs);
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/* IIC controller */
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sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
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sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
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qdev_get_gpio_in(uicdev, 2));
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/* GPIO */
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ppc405_gpio_init(0xef600700);
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/* Serial ports */
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if (serial_hd(0) != NULL) {
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serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
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serial_mm_init(address_space_mem, 0xef600300, 0,
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qdev_get_gpio_in(uicdev, 0),
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PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
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DEVICE_BIG_ENDIAN);
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}
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if (serial_hd(1) != NULL) {
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serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
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serial_mm_init(address_space_mem, 0xef600400, 0,
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qdev_get_gpio_in(uicdev, 1),
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PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
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DEVICE_BIG_ENDIAN);
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}
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/* OCM */
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ppc405_ocm_init(env);
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/* GPT */
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gpt_irqs[0] = pic[19];
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gpt_irqs[1] = pic[20];
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gpt_irqs[2] = pic[21];
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gpt_irqs[3] = pic[22];
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gpt_irqs[4] = pic[23];
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gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
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gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
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gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
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gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
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gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
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ppc4xx_gpt_init(0xef600000, gpt_irqs);
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/* PCI */
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/* Uses pic[3], pic[16], pic[18] */
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/* Uses UIC IRQs 3, 16, 18 */
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/* MAL */
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mal_irqs[0] = pic[11];
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mal_irqs[1] = pic[12];
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mal_irqs[2] = pic[13];
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mal_irqs[3] = pic[14];
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mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
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mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
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mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
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mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
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ppc4xx_mal_init(env, 4, 2, mal_irqs);
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/* Ethernet */
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/* Uses pic[9], pic[15], pic[17] */
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/* Uses UIC IRQs 9, 15, 17 */
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/* CPU control */
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ppc405ep_cpc_init(env, clk_setup, sysclk);
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