From 71db710f7ee00cf324153bbc203e6dad8c99850b Mon Sep 17 00:00:00 2001 From: blueswir1 Date: Fri, 8 Jun 2007 16:45:23 +0000 Subject: [PATCH] Fix incorrect target_ulong use in hw devices git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2962 c046a42c-6fe2-441c-8c8c-71466251a162 --- hw/dma.c | 4 ++-- hw/ds1225y.c | 4 ++-- hw/pckbd.c | 4 ++-- hw/pflash_cfi02.c | 22 +++++++++++----------- hw/ppc405.h | 13 ++++++++----- hw/ppc405_boards.c | 4 ++-- hw/ppc405_uc.c | 25 ++++++++++++++----------- hw/serial.c | 4 ++-- vl.h | 11 ++++++----- 9 files changed, 49 insertions(+), 42 deletions(-) diff --git a/hw/dma.c b/hw/dma.c index ea13eae492..2e8608cfce 100644 --- a/hw/dma.c +++ b/hw/dma.c @@ -383,7 +383,7 @@ void DMA_register_channel (int nchan, int DMA_read_memory (int nchan, void *buf, int pos, int len) { struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; - target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; + target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; if (r->mode & 0x20) { int i; @@ -405,7 +405,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len) int DMA_write_memory (int nchan, void *buf, int pos, int len) { struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; - target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; + target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; if (r->mode & 0x20) { int i; diff --git a/hw/ds1225y.c b/hw/ds1225y.c index 48d6636b3c..7851096fad 100644 --- a/hw/ds1225y.c +++ b/hw/ds1225y.c @@ -33,7 +33,7 @@ typedef enum struct ds1225y_t { - target_ulong mem_base; + target_phys_addr_t mem_base; uint32_t capacity; const char *filename; QEMUFile *file; @@ -99,7 +99,7 @@ static CPUWriteMemoryFunc *nvram_none[] = { }; /* Initialisation routine */ -ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename) +ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename) { ds1225y_t *s; int mem_index1, mem_index2; diff --git a/hw/pckbd.c b/hw/pckbd.c index de508b3090..8f2466d80a 100644 --- a/hw/pckbd.c +++ b/hw/pckbd.c @@ -421,8 +421,8 @@ static CPUWriteMemoryFunc *kbd_mm_write[] = { &kbd_mm_writeb, }; -void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base, - int it_shift) +void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, + target_phys_addr_t base, int it_shift) { KBDState *s = &kbd_state; int s_io_memory; diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index 76e4a1d9b6..f98d11438f 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -50,9 +50,9 @@ do { \ struct pflash_t { BlockDriverState *bs; - target_ulong base; - target_ulong sector_len; - target_ulong total_len; + target_phys_addr_t base; + uint32_t sector_len; + uint32_t total_len; int width; int wcycle; /* if 0, the flash is read normally */ int bypass; @@ -85,9 +85,9 @@ static void pflash_timer (void *opaque) pfl->cmd = 0; } -static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width) +static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width) { - target_ulong boff; + uint32_t boff; uint32_t ret; uint8_t *p; @@ -199,10 +199,10 @@ static void pflash_update(pflash_t *pfl, int offset, } } -static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value, +static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, int width) { - target_ulong boff; + uint32_t boff; uint8_t *p; uint8_t cmd; @@ -219,7 +219,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value, DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__, offset, value, width, pfl->wcycle); if (pfl->wcycle == 0) - offset -= (target_ulong)(long)pfl->storage; + offset -= (uint32_t)(long)pfl->storage; else offset -= pfl->base; @@ -521,14 +521,14 @@ static int ctz32 (uint32_t n) return ret; } -pflash_t *pflash_register (target_ulong base, ram_addr_t off, +pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, BlockDriverState *bs, - target_ulong sector_len, int nb_blocs, int width, + uint32_t sector_len, int nb_blocs, int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3) { pflash_t *pfl; - target_long total_len; + int32_t total_len; total_len = sector_len * nb_blocs; /* XXX: to be fixed */ diff --git a/hw/ppc405.h b/hw/ppc405.h index c491ed55e1..b2624c3861 100644 --- a/hw/ppc405.h +++ b/hw/ppc405.h @@ -83,7 +83,8 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); /* SDRAM controller */ void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, - target_ulong *ram_bases, target_ulong *ram_sizes, + target_phys_addr_t *ram_bases, + target_phys_addr_t *ram_sizes, int do_init); /* Peripheral controller */ void ppc405_ebc_init (CPUState *env); @@ -107,15 +108,17 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio, /* Memory access layer */ void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]); /* PowerPC 405 microcontrollers */ -CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4], +CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], + target_phys_addr_t ram_sizes[4], uint32_t sysclk, qemu_irq **picp, ram_addr_t *offsetp, int do_init); -CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2], +CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], + target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, ram_addr_t *offsetp, int do_init); /* IBM STBxxx microcontrollers */ -CPUState *ppc_stb025_init (target_ulong ram_bases[2], - target_ulong ram_sizes[2], +CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2], + target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, ram_addr_t *offsetp); diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index 2e2ca0e74a..b0be417d32 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -184,7 +184,7 @@ static void ref405ep_init (int ram_size, int vga_ram_size, int boot_device, CPUPPCState *env; qemu_irq *pic; ram_addr_t sram_offset, bios_offset, bdloc; - target_ulong ram_bases[2], ram_sizes[2]; + target_phys_addr_t ram_bases[2], ram_sizes[2]; target_ulong sram_size, bios_size; //int phy_addr = 0; //static int phy_addr = 1; @@ -506,7 +506,7 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size, int boot_device, CPUPPCState *env; qemu_irq *pic; ram_addr_t bios_offset; - target_ulong ram_bases[2], ram_sizes[2]; + target_phys_addr_t ram_bases[2], ram_sizes[2]; target_ulong bios_size; target_ulong kernel_base, kernel_size, initrd_base, initrd_size; int linux_boot; diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index e06165d529..384eb0d3ee 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -903,8 +903,8 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; struct ppc4xx_sdram_t { uint32_t addr; int nbanks; - target_ulong ram_bases[4]; - target_ulong ram_sizes[4]; + target_phys_addr_t ram_bases[4]; + target_phys_addr_t ram_sizes[4]; uint32_t besr0; uint32_t besr1; uint32_t bear; @@ -924,7 +924,7 @@ enum { SDRAM0_CFGDATA = 0x011, }; -static uint32_t sdram_bcr (target_ulong ram_base, target_ulong ram_size) +static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size) { uint32_t bcr; @@ -960,7 +960,7 @@ static uint32_t sdram_bcr (target_ulong ram_base, target_ulong ram_size) return bcr; } -static inline target_ulong sdram_base (uint32_t bcr) +static inline target_phys_addr_t sdram_base (uint32_t bcr) { return bcr & 0xFF800000; } @@ -1206,7 +1206,8 @@ static void sdram_reset (void *opaque) } void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, - target_ulong *ram_bases, target_ulong *ram_sizes, + target_phys_addr_t *ram_bases, + target_phys_addr_t *ram_sizes, int do_init) { ppc4xx_sdram_t *sdram; @@ -1215,10 +1216,10 @@ void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, if (sdram != NULL) { sdram->irq = irq; sdram->nbanks = nbanks; - memset(sdram->ram_bases, 0, 4 * sizeof(target_ulong)); - memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_ulong)); - memset(sdram->ram_sizes, 0, 4 * sizeof(target_ulong)); - memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_ulong)); + memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); + memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t)); + memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); + memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t)); sdram_reset(sdram); qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, @@ -3017,7 +3018,8 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], } } -CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4], +CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], + target_phys_addr_t ram_sizes[4], uint32_t sysclk, qemu_irq **picp, ram_addr_t *offsetp, int do_init) { @@ -3365,7 +3367,8 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], } } -CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2], +CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], + target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, ram_addr_t *offsetp, int do_init) { diff --git a/hw/serial.c b/hw/serial.c index 088886258e..5513007d1a 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -86,7 +86,7 @@ struct SerialState { qemu_irq irq; CharDriverState *chr; int last_break_enable; - target_ulong base; + target_phys_addr_t base; int it_shift; }; @@ -437,7 +437,7 @@ static CPUWriteMemoryFunc *serial_mm_write[] = { &serial_mm_writel, }; -SerialState *serial_mm_init (target_ulong base, int it_shift, +SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr, int ioregister) { diff --git a/vl.h b/vl.h index 7d82bd111d..0ff5109f05 100644 --- a/vl.h +++ b/vl.h @@ -994,7 +994,7 @@ int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num); /* ds1225y.c */ typedef struct ds1225y_t ds1225y_t; -ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename); +ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename); /* es1370.c */ int es1370_init (PCIBus *bus, AudioState *s); @@ -1059,7 +1059,8 @@ void *vmmouse_init(void *m); /* pckbd.c */ void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); -void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base, int it_shift); +void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, + target_phys_addr_t base, int it_shift); /* mc146818rtc.c */ @@ -1074,7 +1075,7 @@ void rtc_set_date(RTCState *s, const struct tm *tm); typedef struct SerialState SerialState; SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr); -SerialState *serial_mm_init (target_ulong base, int it_shift, +SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr, int ioregister); uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr); @@ -1485,9 +1486,9 @@ int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); extern BlockDriverState *pflash_table[MAX_PFLASH]; typedef struct pflash_t pflash_t; -pflash_t *pflash_register (target_ulong base, ram_addr_t off, +pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, BlockDriverState *bs, - target_ulong sector_len, int nb_blocs, int width, + uint32_t sector_len, int nb_blocs, int width, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3);